DCT
3:22-cv-01794
Bell Semiconductor LLC v. NXP USA Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: NXP USA, Inc. (Texas)
- Plaintiff’s Counsel: Patterson Law Group, APC; McKool Smith, P.C.; Devlin Law Firm LLC
- Case Identification: 3:22-cv-01794, S.D. Cal., 11/15/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains a regular and established place of business in the district, employs a significant number of engineers there, and advertises for local positions related to the patented technologies.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor design processes, used to create products such as the NXP LS1043A Quad-Core Networking Processor, infringe a patent related to methods for reducing electrical interference between layers in an integrated circuit.
- Technical Context: The technology addresses a challenge in semiconductor manufacturing where "dummy fill" material, added to ensure planarity, can inadvertently create parasitic capacitance between layers, degrading chip performance.
- Key Procedural History: The complaint states that an exemplary infringement analysis and an expert declaration are attached as exhibits, though these exhibits were not publicly filed with the complaint itself. The complaint heading for Count I contains a scrivener's error, referencing U.S. Patent No. 6,436,807, while the body of the complaint, the prayer for relief, and all substantive allegations exclusively concern U.S. Patent No. 7,396,760.
Case Timeline
| Date | Event |
|---|---|
| 2004-11-17 | Priority Date for U.S. Patent No. 7,396,760 |
| 2008-07-08 | U.S. Patent No. 7,396,760 Issued |
| 2022-11-15 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,396,760 - "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits"
- Patent Identification: U.S. Patent No. 7,396,760, "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits," issued July 8, 2008. (Compl. ¶¶24, 27).
The Invention Explained
- Problem Addressed: The patent’s background explains that conventional methods for placing "dummy fill" material in integrated circuits focused on achieving uniform density for manufacturing processes like chemical mechanical polishing (CMP) on a layer-by-layer basis. (Compl. ¶¶4-5; ’760 Patent, col. 1:56-66). This approach ignored the negative effects of dummy fill features on one layer overlapping with those on an adjacent layer, which creates unwanted "bulk capacitance" that can slow down circuit timing and degrade performance. (Compl. ¶¶6-7; ’760 Patent, col. 2:1-6).
- The Patented Solution: The invention describes a method that analyzes successive layers as a pair to identify and minimize the overlap between their respective dummy fill areas. ('760 Patent, col. 2:16-19). By determining the overlap and then "re-arranging" the dummy fill features—for example, into an offset or "checkerboard pattern"—the method aims to reduce the harmful interlayer bulk capacitance that was a byproduct of prior art techniques. (Compl. ¶9; ’760 Patent, col. 4:30-45; Fig. 3).
- Technical Importance: This "intelligent dummy fill placement" provided a way to improve circuit speed and performance by directly addressing a source of parasitic capacitance that conventional, density-focused methodologies failed to consider. (Compl. ¶10).
Key Claims at a Glance
- The complaint asserts "one or more claims" and specifically quotes independent Claim 1. (Compl. ¶¶31, 38).
- Independent Claim 1 recites a method with the following essential elements:
- obtaining layout information of an integrated circuit having multiple layers;
- obtaining a first dummy fill space for a first layer;
- obtaining a second dummy fill space for a successive second layer;
- determining an overlap between the first and second dummy fill spaces; and
- minimizing the overlap by re-arranging dummy fill features in both spaces, where the dummy fill consists of non-signal carrying lines. (Compl. ¶31).
- The complaint’s general allegation of infringing "one or more claims" suggests the right to assert other claims, including dependent claims, is reserved. (Compl. ¶38).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Processes" as the design methodologies used by NXP to create semiconductor layouts. (Compl. ¶39). The NXP LS1043A Quad-Core Networking Processor is identified as one example of a product made using these allegedly infringing processes. (Compl. ¶9).
Functionality and Market Context
- The complaint alleges that NXP utilizes a variety of commercial design tools from vendors like Cadence, Synopsys, and Siemens to implement the Accused Processes. (Compl. ¶39). These processes are alleged to perform "arrangement and rearrangement of dummy fill in a timing aware fashion," which includes the ability to "stagger the dummy fill in successive layers so as to minimize the interlayer bulk capacitance after determining their overlap." (Compl. ¶39). The complaint does not provide further details on the specific operation of these processes or the market positioning of the example product.
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
Claim Chart Summary
- The complaint does not include a claim chart, but its narrative allegations for Claim 1 can be summarized as follows.
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method for placing dummy fill patterns in an integrated circuit fabrication process, comprising: | NXP is alleged to use a "patented methodology to design one or more semiconductor devices." | ¶38, ¶39 | col. 6:7-9 |
| obtaining layout information of the integrated circuit... | NXP allegedly "employs a variety of design tools... to make a layout for an interconnect layer of a semiconductor device." | ¶39 | col. 6:10-12 |
| obtaining a first dummy fill space for a first layer... | This is implicitly alleged in NXP's process of arranging and rearranging dummy fill in successive layers. | ¶39 | col. 6:12-14 |
| obtaining a second dummy fill space for a second layer, the second layer being placed successively... | NXP’s processes are alleged to arrange dummy fill in "successive layers." | ¶39 | col. 6:14-16 |
| determining an overlap between the first dummy fill space and the second dummy fill space | The complaint alleges NXP's processes minimize capacitance "after determining their overlap." | ¶39 | col. 6:17-18 |
| minimizing the overlap by re-arranging a plurality of first dummy fill features and... second dummy fill features | NXP's Accused Processes allegedly "allow arrangement and rearrangement of dummy fill... including with the ability to stagger the dummy fill in successive layers so as to minimize the interlayer bulk capacitance." | ¶39 | col. 6:19-22 |
| wherein the first dummy fill space includes non-signal carrying lines... | This is inherent in the allegation of placing "dummy fill," which by definition is non-functional. The complaint discusses the nature of dummy fill extensively. | ¶5, ¶6, ¶9 | col. 6:23-26 |
Identified Points of Contention
- Scope Questions: A central question may be whether the term "re-arranging" requires a discrete, separate action as depicted in the patent's flowchart (Fig. 3), or if it can be read to cover the output of a holistic optimization algorithm within a modern design tool that may not follow the same sequence of steps.
- Technical Questions: An evidentiary question will be what proof exists that NXP's processes perform the specific claimed sequence of first "determining an overlap" and then "minimizing the overlap by re-arranging." The defense may argue that the accused commercial design tools achieve a similar outcome through different, more complex optimization routines that do not map one-to-one with the patent's claimed method steps.
V. Key Claim Terms for Construction
The Term: "re-arranging"
- Context and Importance: This is the active, corrective step at the core of the claimed invention. Its definition will be critical to determining whether the operations performed by NXP's accused design tools fall within the scope of the claim.
- Intrinsic Evidence for a Broader Interpretation: The specification describes the goal as minimizing overlaps, and "re-arranging" is the mechanism. A party could argue that any process that alters an initial dummy fill layout to achieve this goal constitutes "re-arranging." The claim language itself is not explicitly limited to a specific algorithm. ('760 Patent, col. 6:19-22).
- Intrinsic Evidence for a Narrower Interpretation: The patent repeatedly uses a "checkerboard pattern" as the prime example of a re-arranged layout. ('760 Patent, col. 4:40-45; col. 4:50-51; Fig. 4). A party could argue that "re-arranging" should be construed as being limited to or at least informed by this specific, disclosed embodiment of creating an offset pattern, rather than any general optimization.
The Term: "minimizing the overlap"
- Context and Importance: This term defines the purpose and result of the "re-arranging" step. Practitioners may focus on this term because its construction will set the standard for what the accused process must achieve to be found infringing (e.g., any reduction vs. an optimal reduction).
- Intrinsic Evidence for a Broader Interpretation: The abstract states the invention is for "intelligent dummy filling placement to reduce inter-layer capacitance," and the patent consistently discusses the benefit of reducing or eliminating unwanted capacitance. ('760 Patent, Abstract; col. 2:7-9). This may support a construction where "minimizing" means achieving any meaningful reduction in overlap compared to a baseline placement.
- Intrinsic Evidence for a Narrower Interpretation: The term "minimize" could be argued to imply an optimization process that seeks the lowest possible value, not just any reduction. The patent's description of a discrete method (Fig. 3) where overlap is determined and then features are re-arranged could support an argument that the term requires a targeted process designed to achieve a near-optimal result, not just an incidental reduction from a general placement algorithm.
VI. Other Allegations
The complaint does not contain specific counts or factual allegations supporting indirect or willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of "process equivalence": does the functionality of the commercial electronic design automation (EDA) tools used by NXP map directly onto the sequential method steps recited in Claim 1? The case may depend on whether NXP's use of these tools constitutes a holistic optimization that achieves a similar outcome, or if it can be proven to perform the discrete sequence of "determining" and then "re-arranging to minimize" that specific, determined overlap.
- The case will also present a significant "evidentiary question" regarding the internal workings of NXP's proprietary design flows. As the complaint's allegations are based on "information and belief" regarding the function of these complex software tools, the outcome will likely hinge on technical evidence and expert testimony derived from discovery that can precisely detail how the accused processes operate.