DCT
1:22-cv-02696
Bell Semiconductor LLC v. Phison Electronics Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Phison Electronics, Inc. (Taiwan)
- Plaintiff’s Counsel: McKool Smith, P.C.
- Case Identification: 1:22-cv-02696, D. Colo., 01/03/2023
- Venue Allegations: Plaintiff alleges venue is proper in the District of Colorado because Defendant maintains a "regular and established place of business" in the district, specifically an SSD Engineering Lab in Broomfield, has committed acts of infringement in the district, and employs engineers in the state.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor chip design processes infringe a patent related to efficiently implementing engineering change orders in integrated circuit (IC) designs.
- Technical Context: The technology concerns methods for modifying complex IC designs, a process where efficiency is critical to reducing development costs and accelerating time-to-market in the competitive semiconductor industry.
- Key Procedural History: This First Amended Complaint was filed on January 3, 2023. Plaintiff Bell Semiconductor states it is a successor to the pioneering efforts of Bell Labs and owns a large portfolio of patents developed by companies including Lucent Technologies, Agere Systems, and LSI Corporation.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | U.S. Patent No. 7,231,626 Priority Date (Application Filed) |
| 2007-06-12 | U.S. Patent No. 7,231,626 Issued |
| 2023-01-03 | First Amended Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows,”
- Patent Identification: U.S. Patent No. 7,231,626 (“the ’626 Patent”), “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows,” issued on June 12, 2007. (Compl. ¶18).
The Invention Explained
- Problem Addressed: The patent describes prior art methods for making changes to an IC design as highly inefficient. When an engineering change order (ECO) was issued, design tools had to be run on the entire circuit design, even for a minor modification. This process could take approximately one week, regardless of the change's size, because the analysis time scaled with the size of the entire circuit, not the size of the change. (’626 Patent, col. 2:14-22, 2:36-44; Compl. ¶¶ 23-24).
- The Patented Solution: The invention proposes a method to localize the design revision process. It involves creating a "window"—a defined sub-region of the IC design that encloses the required change. Subsequent processing steps, such as routing electrical connections ("nets"), are then performed only within this limited window. The updated window is then merged back into a copy of the full design, creating a revised IC design without reprocessing the unchanged portions. (’626 Patent, Abstract; col. 4:5-24; Fig. 2).
- Technical Importance: This localized approach promised significant savings in the time and computational resources required for routing, design rule verification, and other intensive tasks, thereby shortening the overall design timeline and reducing costs. (’626 Patent, col. 3:18-23; Compl. ¶¶ 25-26).
Key Claims at a Glance
- The complaint asserts infringement of one or more claims, with a focus on independent Claim 1. (Compl. ¶¶ 29, 36).
- The essential elements of Claim 1 are:
- (a) receiving as input an integrated circuit design;
- (b) receiving as input an engineering change order to the integrated circuit design;
- (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design;
- (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window;
- (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and
- (f) generating as output the revised integrated circuit design.
- The patent also includes an independent claim (Claim 5) directed to a computer-readable medium embodying instructions to perform a similar method. (’626 Patent, col. 7:16-25, col. 8:1-12).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Phison Accused Product" as at least the PS2251-17-43 semiconductor chip. (Compl. ¶1). More broadly, the infringing instrumentalities are the "Accused Processes"—the design methodologies Phison allegedly uses to design its semiconductor devices. (Compl. ¶37).
Functionality and Market Context
- The complaint alleges that Phison uses a variety of third-party design tools from vendors such as Cadence, Synopsys, and/or Siemens to implement ECOs. (Compl. ¶37). These "Accused Processes" are alleged to perform "incremental routing" by routing only the nets affected by an ECO and then merging that "changed area" into the overall circuit layout to create a revised design. (Compl. ¶37). The complaint further alleges that related processes, such as parasitic extraction and design rule checks, are also performed only for nets within the window defined by the ECO. (Compl. ¶¶ 38-39). The complaint asserts that these efficiency gains are of significant commercial value to chip designers like Phison. (Compl. ¶27).
- No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
Claim Chart Summary
- The complaint alleges that Phison's design processes, used to create products like the PS2251-17-43, practice the method of Claim 1. The following table summarizes the allegations.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | Phison’s design process for its semiconductor products, including the Accused Product, necessarily receives an IC design as input. | ¶37 | col. 2:54-56 |
| (b) receiving as input an engineering change order to the integrated circuit design; | Phison’s process for implementing an ECO receives the ECO as an input to modify the IC design. | ¶37 | col. 2:57 |
| (c) creating at least one window in the integrated circuit design that encloses a change ... wherein the window ... is less than an entire area of the integrated circuit design; | Phison's process allegedly defines a "changed area" for performing incremental routing that is smaller than the entire circuit layout. | ¶37 | col. 4:58-62 |
| (d) performing an incremental routing ... only for each net ... that is enclosed by the window; | Phison allegedly employs design tools to perform "incremental routing" that is limited to "only routing the nets affected by the ECO." | ¶37 | col. 4:5-8 |
| (e) replacing an area in a copy of the integrated circuit design ... with results of the incremental routing to generate a revised integrated circuit design; | Phison’s process allegedly involves "merging that changed area into the overall circuit layout ... to generate a revised integrated circuit design." | ¶37 | col. 4:20-24 |
| (f) generating as output the revised integrated circuit design. | The alleged process results in the output of a "revised integrated circuit design." | ¶37 | col. 4:20-24 |
Identified Points of Contention
- Scope Questions: The complaint alleges infringement through the use of standard third-party electronic design automation (EDA) tools. (Compl. ¶37). This raises the question of whether Phison's specific use and configuration of these commercially available tools constitutes practicing the patented method, or if the tools operate in a fundamentally different, non-infringing manner.
- Technical Questions: The complaint alleges Phison's process involves a "changed area" and routing "only the nets affected by the ECO." (Compl. ¶37). A key technical question will be what evidence demonstrates that this process is equivalent to creating a "window" bounded by "coordinates" and routing only nets "enclosed by the window," as the claim requires. The court may need to determine if Phison's process relies on a geometric, coordinate-based boundary as described in the patent, or a different logical or connectivity-based method for isolating changes.
V. Key Claim Terms for Construction
The Term: "window"
- Context and Importance: This term is foundational to the patent's claim of efficiency, as it defines the limited area where work is performed. The construction of "window" will be critical for determining whether the "changed area" in Phison's alleged process (Compl. ¶37) falls within the claim's scope.
- Intrinsic Evidence for a Broader Interpretation: The specification provides a general definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design." (’626 Patent, col. 4:58-62). This could support an interpretation where any defined sub-region qualifies.
- Intrinsic Evidence for a Narrower Interpretation: The patent also describes a specific method for creating windows by calculating a "bounding box" around the "port instances for each net changed." (’626 Patent, col. 4:54-57; Fig. 3). A defendant could argue that a "window" is not just any sub-region but must be a geometric construct defined by coordinates, as depicted in Figure 4 and generated through a process like the one described in the embodiment. (’626 Patent, Fig. 4; col. 5:17-23).
The Term: "incremental routing"
- Context and Importance: This term defines the core action of the claimed method. Practitioners may focus on this term because the infringement analysis depends on whether the functionality of the EDA tools allegedly used by Phison (Compl. ¶37) meets the specific meaning of "incremental routing" as used in the patent.
- Intrinsic Evidence for a Broader Interpretation: The patent primarily contrasts the invention with performing "a routing of the entire integrated circuit design." (’626 Patent, col. 2:64-65). This might support a broad construction where any routing of less than the full design is considered "incremental."
- Intrinsic Evidence for a Narrower Interpretation: The specification states that in the inventive method, "only the nets that are modified by the engineering change order are routed." (’626 Patent, col. 4:6-8). This could support a narrower definition requiring that the routing process be strictly limited to nets physically contained within the geometric "window," as opposed to any process that logically re-routes only affected nets, which may have connections extending beyond a defined window.
VI. Other Allegations
- Indirect Infringement: The complaint focuses on direct infringement under 35 U.S.C. § 271(a) and does not plead specific facts to support claims of induced or contributory infringement. (Compl. ¶36).
- Willful Infringement: The complaint does not use the term "willful." It does allege that Phison's infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285. (Compl. ¶43). The complaint does not contain allegations of pre-suit knowledge of the ’626 Patent.
VII. Analyst’s Conclusion: Key Questions for the Case
- A key evidentiary question will be one of "process mapping": What specific, verifiable steps do Phison's "Accused Processes" (Compl. ¶37) perform when implementing an ECO with third-party EDA tools, and does that operational sequence map onto each limitation of the asserted claims? The complaint's high-level allegations will require substantiation with detailed evidence of Phison's actual design workflow.
- A core legal issue will be one of "definitional scope": Can the term "window", which is described in embodiments as a geometric "bounding box" defined by coordinates (’626 Patent, Fig. 3, Fig. 4), be construed to cover any logically defined "changed area" (Compl. ¶37) that Phison's EDA tools may use to perform localized operations? The court's construction of this term may be dispositive of the infringement analysis.