DCT

1:11-cv-00307

Infineon Tech AG v. Atmel Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:11-cv-00307, D. Del., 04/11/2011
  • Venue Allegations: Venue is alleged based on Defendant Atmel being a Delaware corporation that regularly conducts business in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s microcontroller products infringe eleven patents related to semiconductor manufacturing processes, circuit design, power management, processor architecture, and debug interfaces.
  • Technical Context: The dispute involves microcontrollers, which are integrated circuits that serve as the core processing components in a vast range of modern electronic devices, from automotive systems to consumer electronics.
  • Key Procedural History: The complaint alleges that for several of the asserted patents, Defendant had pre-suit knowledge of infringement based on written notice and meetings where the specific patents and infringement were discussed, forming the basis for allegations of willful infringement. The complaint also seeks declaratory judgment of non-infringement and invalidity for three patents asserted by Atmel against Infineon, indicating a broader, ongoing business dispute between the two semiconductor companies.

Case Timeline

Date Event
1993-01-19 U.S. Patent No. 5,422,309 Priority Date
1993-05-03 U.S. Patent No. 5,539,910 Priority Date
1995-06-06 U.S. Patent No. 5,422,309 Issues
1995-09-19 U.S. Patent No. 5,739,708 Priority Date
1996-07-23 U.S. Patent No. 5,539,910 Issues
1997-09-12 U.S. Patent No. 6,076,159 Priority Date
1998-04-14 U.S. Patent No. 5,739,708 Issues
1998-08-06 U.S. Patent No. 6,769,065 Priority Date
1998-10-15 U.S. Patent No. 6,788,235 Priority Date
1999-08-02 U.S. Patent No. 6,653,963 Priority Date
2000-02-29 U.S. Patent No. 6,665,802 Priority Date
2000-06-13 U.S. Patent No. 6,076,159 Issues
2001-04-20 U.S. Patent No. 7,281,162 Priority Date
2001-05-23 U.S. Patent No. 7,000,148 Priority Date
2003-05-22 U.S. Patent No. 7,149,926 Priority Date
2003-11-25 U.S. Patent No. 6,653,963 Issues
2003-12-16 U.S. Patent No. 6,665,802 Issues
2004-07-27 U.S. Patent No. 6,769,065 Issues
2004-09-07 U.S. Patent No. 6,788,235 Issues
2006-02-14 U.S. Patent No. 7,000,148 Issues
2006-12-12 U.S. Patent No. 7,149,926 Issues
2007-10-09 U.S. Patent No. 7,281,162 Issues
2011-04-11 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,422,309 - Method For Producing a Metallization Level Having Contacts and Interconnects Connecting the Contacts

  • Issued: June 6, 1995.
  • The Invention Explained:
    • Problem Addressed: The patent's background section describes the challenge of creating reliable electrical connections within increasingly miniaturized integrated circuits, specifically noting that the boundary between vertical contacts and horizontal interconnects can create undesirable electrical resistance and structural weaknesses (’309 Patent, col. 1:14-41).
    • The Patented Solution: The invention proposes a manufacturing method where trenches for interconnects and holes for contacts are etched into an insulating layer and then filled with metal in a single, unified step. This is achieved by first opening the contact holes, filling them with a temporary photoresist, using a second mask to etch the interconnect trenches, and then removing the photoresist and depositing metal into the entire combined structure at once, thereby creating a seamless, monolithic conductor. (’309 Patent, Abstract; col. 4:59-col. 5:12).
    • Technical Importance: This type of process, related to what is known as dual damascene fabrication, is important for improving the performance and reliability of high-density semiconductor devices by eliminating a key point of failure in the wiring layers. (’309 Patent, col. 1:14-21).
  • Key Claims at a Glance:
    • The complaint asserts infringement of "one or more claims" without specifying them (Compl. ¶18). Independent method claim 1 is representative.
    • Essential elements of claim 1 include:
      • Applying an insulating layer to a substrate.
      • Opening contact holes in the insulating layer.
      • Producing an "interconnect mask" by covering the layer with photoresist that also fills the contact holes, then developing it to uncover areas for interconnects while leaving the holes filled.
      • Using the interconnect mask to etch trenches into the insulating layer.
      • Removing the photoresist and filling both the trench and contact holes with metal.
    • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 5,539,910 - Circuit Configuration For Monitoring the Supply Voltage of a Processor Unit

  • Issued: July 23, 1996.
  • The Invention Explained:
    • Problem Addressed: The patent addresses operational problems in battery-powered electronics, where activating a processor at too low a supply voltage, or a voltage drop during startup, can cause the processor to enter an undefined state, leading to malfunction and excessive power drain (’910 Patent, col. 1:17-34).
    • The Patented Solution: The invention is a two-stage voltage monitoring circuit. An "undervoltage detector" functions at very low voltages to hold the processor in a reset state. Once the supply voltage rises past a certain threshold, a more accurate "comparator" is enabled, which only generates an "activation signal" for the processor when the voltage is safely above the minimum required for stable operation. (’910 Patent, Abstract; col. 3:33-44).
    • Technical Importance: This tiered approach improves the startup reliability and power efficiency of battery-operated devices by preventing the processor from attempting to operate in an unstable voltage condition. (’910 Patent, col. 2:5-10).
  • Key Claims at a Glance:
    • The complaint asserts infringement of "one or more claims" without specification (Compl. ¶22). Independent claim 1 is representative.
    • Essential elements of claim 1 include:
      • An undervoltage detector generating a reset signal within a first voltage range below the minimum supply voltage.
      • A comparator generating an activation signal only when the supply voltage is above a third, higher limit which is above the minimum supply voltage.
      • An oscillator that operates above a second limit value (between the first and third limits).
      • A processor unit that operates only upon receiving the activation signal.
    • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 5,739,708 - Circuit Configuration For Generating an Enable Signal For a Clock-Controllable Circuit

  • Issued: April 14, 1998.
  • Technology Synopsis: The patent describes a circuit to ensure a clock-controllable circuit, such as a microprocessor, is not enabled until its clock source (e.g., a quartz oscillator) has achieved a stable frequency and amplitude. It uses a level weighting device and a counter to delay the enable signal until a predetermined number of stable clock cycles have passed, preventing malfunctions caused by an unstable initial clock signal.
  • Asserted Claims: "one or more claims" (Compl. ¶26).
  • Accused Features: Atmel's 32-bit AVR microcontroller products (Compl. ¶26).

U.S. Patent No. 6,076,159 - Execution of a Loop Instructing in a Loop Pipeline After Detection of a First Occurrence of the Loop Instruction in an Integer Pipeline

  • Issued: June 13, 2000.
  • Technology Synopsis: The patent discloses a processor architecture designed to accelerate the execution of program loops. It features multiple execution pipelines; a loop instruction is first detected in a general-purpose integer pipeline, and then subsequent iterations of the loop are executed in a specialized, more efficient loop pipeline.
  • Asserted Claims: "one or more claims" (Compl. ¶30).
  • Accused Features: Atmel's 32-bit AVR microcontroller products (Compl. ¶30).

U.S. Patent No. 6,653,963 - Method and Apparatus for the A/D Conversion of Analog Signals and Corresponding A/D Converter Arrangement

  • Issued: November 25, 2003.
  • Technology Synopsis: The invention relates to an analog-to-digital (A/D) converter system where key operating parameters—such as resolution, sampling time, and conversion time—can be set on a channel-specific basis. This allows a single A/D converter arrangement to be flexibly configured to handle various types of analog signals, each with different conversion requirements.
  • Asserted Claims: "one or more claims" (Compl. ¶34).
  • Accused Features: Atmel's 8-bit AVR microcontroller products (Compl. ¶34).

U.S. Patent No. 6,665,802 - Power Management and Control for a Microcontroller

  • Issued: December 16, 2003.
  • Technology Synopsis: The patent describes a modular and decentralized power management system for a microcontroller. A central power management state machine issues global power mode commands (e.g., RUN, IDLE, SLEEP), but each subsystem contains its own software configurable register that allows its response to these commands to be independently controlled and optimized.
  • Asserted Claims: "one or more claims" (Compl. ¶38).
  • Accused Features: Atmel's 8-bit and 32-bit AVR microcontroller products (Compl. ¶38).

U.S. Patent No. 6,769,065 - Access Authorization Device For Controlling Access Requested by an OCDS Module

  • Issued: July 27, 2004.
  • Technology Synopsis: The invention provides a security mechanism for on-chip debug support (OCDS) modules. It describes an access authorization controller that requires an external debugger to verify its authorization before it is granted access to read or write to sensitive internal registers and memory, thereby preventing misuse of the powerful debug interface.
  • Asserted Claims: "one or more claims" (Compl. ¶42).
  • Accused Features: Atmel's 32-bit AVR microcontroller products (Compl. ¶43).

U.S. Patent No. 6,788,235 - A/D Converter Having Signaling and Requesting Capability

  • Issued: September 7, 2004.
  • Technology Synopsis: This patent discloses a system where multiple A/D converters can synchronize their operations directly with each other without requiring a central controller. One A/D converter can signal the start of its conversion process to another or request a conversion from another, enabling precisely time-synchronized sampling of multiple analog signals.
  • Asserted Claims: "one or more claims" (Compl. ¶46).
  • Accused Features: Atmel's 8-bit AVR microcontroller products (Compl. ¶46).

U.S. Patent No. 7,000,148 - Program-Controlled Unit

  • Issued: February 14, 2006.
  • Technology Synopsis: The patent describes a microcontroller architecture in which debug resources are connected to peripheral units via a second, dedicated internal bus. This allows trace data to be routed from the debug system through existing peripheral interfaces (e.g., USB, Ethernet) to an external device, eliminating the need for a separate, dedicated debug port and preventing interference with the main CPU bus.
  • Asserted Claims: "one or more claims" (Compl. ¶50).
  • Accused Features: Atmel's 32-bit AVR microcontroller products (Compl. ¶50).

U.S. Patent No. 7,149,926 - Configurable Real-Time Trace Port For Embedded Processors

  • Issued: December 12, 2006.
  • Technology Synopsis: The invention describes a programmable trace port for debugging embedded processors that filters and compresses trace information before sending it to an external debugger. This selective filtering, based on user-defined trigger events, reduces the volume of data and helps prevent buffer over-runs that can occur when the processor generates trace data faster than it can be transmitted off-chip.
  • Asserted Claims: "one or more claims" (Compl. ¶54).
  • Accused Features: Atmel's 32-bit AVR microcontroller products (Compl. ¶54).

U.S. Patent No. 7,281,162 - Program-Controlled Unit

  • Issued: October 9, 2007.
  • Technology Synopsis: This patent discloses a method where trace information generated by a microcontroller's core is stored or output along with corresponding identification codes. These codes, defined by the software program being debugged, allow an external system to identify the nature of the trace data (e.g., which variable it represents) without requiring complex on-chip hardware for that purpose.
  • Asserted Claims: "one or more claims" (Compl. ¶58).
  • Accused Features: Atmel's 32-bit AVR microcontroller products (Compl. ¶58).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies several categories of Atmel's microcontroller products (Compl. ¶¶ 18, 22, 26, 30, 34, 38, 43, 46, 50, 54, 58). These include:
    • Atmel's AT91SAM9263 products
    • Atmel's 8-bit AVR microcontroller products
    • Atmel's 32-bit AVR microcontroller products

Functionality and Market Context

  • The complaint describes Atmel as being "engaged in the business of designing, developing, and selling microcontroller technologies" (Compl. ¶3). The accused products are integrated circuits that function as the central processing components in various electronic systems.
  • The complaint does not provide specific technical details about the functionality of the accused products. Instead, it makes general allegations that the manufacture or operation of these product families infringes the asserted patents (e.g., Compl. ¶¶ 18, 22).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’309 Patent Infringement Allegations

  • The complaint does not provide sufficient detail for analysis in a claim chart format. The infringement theory is a conclusory statement that Atmel's manufacture, use, or sale of its microcontroller products, such as the AT91SAM9263 products, infringes one or more claims of the ’309 Patent (Compl. ¶18).
  • Identified Points of Contention:
    • Factual Question: A central question will be whether Atmel’s semiconductor fabrication process for the accused microcontrollers includes all steps of the claimed method. As this information is highly proprietary, this would require extensive discovery.
    • Scope Questions: The dispute may turn on the definition of specific process steps, such as whether Atmel’s method for creating an interconnect mask involves "leaving said contact holes filled with photoresist" in the manner required by claim 1.

’910 Patent Infringement Allegations

  • The complaint does not provide sufficient detail for analysis in a claim chart format. The infringement theory is a conclusory statement that Atmel's microcontroller products, such as its 32-bit AVR products, contain circuitry that infringes one or more claims of the ’910 Patent (Compl. ¶22).
  • Identified Points of Contention:
    • Technical Question: An evidentiary issue will be whether the accused products’ power-on and voltage monitoring circuits perform the specific two-stage function required by the claims.
    • Scope Questions: The analysis may focus on whether the accused devices contain two structurally and functionally distinct components corresponding to the claimed "undervoltage detector" and "comparator," or a single integrated circuit. If the latter, a question for the court would be whether that single circuit can meet both claim limitations.

V. Key Claim Terms for Construction

U.S. Patent No. 5,422,309 - Method For Producing a Metallization Level Having Contacts and Interconnects Connecting the Contacts

  • The Term: "developing said photoresist layer to leave said contact holes filled with photoresist" (from claim 1).
  • Context and Importance: This step is central to the invention's method of creating a seamless conductor. The manner in which the photoresist is developed to simultaneously uncover interconnect areas while preserving the resist plugs in the contact holes is a key technical detail. Practitioners may focus on this term because different photolithography techniques could achieve a similar outcome without strictly meeting this limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language does not specify the type of photoresist or the exact mechanism of development, which could support an interpretation covering any development process that results in filled contact holes.
    • Evidence for a Narrower Interpretation: The specification discusses achieving this result "by an appropriately shortened developing time of the photoresist" (’309 Patent, col. 4:5-7) and mentions a specific "two-layer resist system" (’309 Patent, col. 6:42-47). This may suggest the claim is limited to such specific techniques.

U.S. Patent No. 5,539,910 - Circuit Configuration For Monitoring the Supply Voltage of a Processor Unit

  • The Term: "undervoltage detector" and "comparator" (from claim 1).
  • Context and Importance: The claim requires two separate functional blocks, each operating based on different voltage thresholds. The core of the infringement question will be whether Atmel's products contain two such distinct circuits. Practitioners may focus on these terms because modern microcontrollers often integrate voltage supervision into a single, complex power management unit.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The terms are functional. A party could argue that if a single circuit performs the distinct functions of both generating a reset signal in a low-voltage range and an activation signal in a higher-voltage range, it meets the limitations.
    • Evidence for a Narrower Interpretation: The specification and claims describe the two components as operating sequentially and conditionally; the comparator is turned on only "if the reset signal Rs is absent" (’910 Patent, col. 3:37-39), implying they are separate entities. The abstract also lists them as two distinct elements of the configuration.

VI. Other Allegations

Indirect Infringement

  • The complaint includes boilerplate allegations of active inducement and contributory infringement for all asserted patents (e.g., Compl. ¶¶ 18, 22). However, it does not plead specific facts to support these allegations, such as identifying instructions or user manuals that would direct others to infringe.

Willful Infringement

  • The complaint alleges willful infringement for U.S. Patent Nos. 5,422,309, 6,076,159, 6,653,963, 6,665,802, 6,788,235, and 7,000,148. The basis for these allegations is Defendant's alleged "actual knowledge" of the patents and infringement claims from "written notice and at least one or more meetings between Atmel and Infineon AG" where the specific patents were discussed prior to the lawsuit (Compl. ¶¶ 19, 31, 35, 39, 47, 51).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of evidentiary proof: The complaint, filed under older pleading standards, lacks specific factual allegations mapping accused products to claim elements. The case will therefore depend heavily on discovery to ascertain the actual structure and manufacturing processes of Atmel's microcontrollers and whether they align with the technologies claimed across the eleven asserted patents.
  • A second key question will be one of structural and functional correspondence: For the numerous apparatus patents, the dispute will likely center on whether the integrated circuits within Atmel's microcontrollers contain the specific, distinct functional blocks recited in the claims (e.g., a separate "undervoltage detector" and "comparator" in the ’910 patent), or whether Atmel’s products achieve similar results using a different, non-infringing architecture.
  • A final central question concerns the scope of the dispute: The assertion of a broad, 11-patent portfolio covering disparate aspects of semiconductor technology suggests this is not a dispute over a single feature but a major portfolio-level conflict. The resolution may depend less on the merits of any single patent and more on the cumulative strength of the portfolio and the parties' strategic interests in the wider business relationship.