DCT
1:15-cv-00368
Visual Memory LLC v. Freescale Semiconductor Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Visual Memory LLC (Delaware)
- Defendant: Freescale Semiconductor, Inc. (Delaware)
- Plaintiff’s Counsel: Stamoulis & Weinblatt LLC
- Case Identification: 1:15-cv-00368, D. Del., 05/08/2015
- Venue Allegations: Venue is asserted based on the defendant conducting substantial business within the District of Delaware, which allegedly includes at least a portion of the infringing activities.
- Core Dispute: Plaintiff alleges that Defendant’s i.MX53xD Applications Processors infringe a patent related to memory devices capable of performing multiple, selectable types of data access within a single memory cycle.
- Technical Context: The technology concerns high-performance memory architectures designed to optimize data processing in systems with diverse computational demands, such as those combining complex graphics processing with routine display refresh operations.
- Key Procedural History: The complaint does not reference any prior litigation, Inter Partes Review (IPR) proceedings, licensing history, or significant prosecution events related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 1995-10-04 | '932 Patent Priority Date |
| 1997-08-05 | '932 Patent Issue Date |
| 2015-05-08 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 5,654,932 - "Memory Devices With Selectable Access Type And Methods Using The Same," issued August 5, 1997
The Invention Explained
- Problem Addressed: The patent’s background section describes an inefficiency in conventional computer memory systems. Different processing tasks are best served by different types of memory access (e.g., random, page, or serial), but existing memory devices could not efficiently switch between these modes, often requiring a delay to initiate a new Row Address Strobe (RAS) cycle to change modes (’932 Patent, col. 1:60–2:6).
- The Patented Solution: The invention proposes a memory device with an array of memory cells partitioned into distinct groups of columns. These different groups are coupled to different types of access circuitry. For example, one group of columns may be accessed via standard column decoders to perform random or page-mode access, while another group is accessed via shift registers to perform serial access. This architecture enables the memory to handle multiple access types, either in quick succession or simultaneously, within a single RAS cycle (’932 Patent, col. 2:21–39; Fig. 2).
- Technical Importance: This architecture aimed to enhance overall system performance by allowing a processor to select the most efficient memory access type for a given operation "on-the-fly" without the performance penalty associated with changing modes in prior art memories (’932 Patent, col. 1:46–59).
Key Claims at a Glance
The complaint alleges infringement of "one or more claims" of the '932 patent without further specification (Compl. ¶10). The patent contains several independent claims, including Claims 1 and 12, which appear to cover distinct embodiments of the invention.
Independent Claim 1: The essential elements of this claim include:
- An array of rows and columns of memory cells.
- Row decoder circuitry for selecting a row.
- First column decoder circuitry for selecting a location in a first group of columns.
- Second column decoder circuitry for selecting a location in a second group of columns.
- Control circuitry that is "operable during a selected random cycle to initiate a page access" through one of the column decoders and a random access through the other.
Independent Claim 12: The essential elements of this claim include:
- An array of rows and columns of memory cells.
- Row decoder circuitry for selecting a row.
- Column decoder circuitry for selecting a location in a first group of columns.
- "At least one shift register for providing serial access" to cells within a second group of columns.
III. The Accused Instrumentality
Product Identification
- The complaint identifies Freescale Semiconductor's "i.MX53xD Applications Processors" as the infringing instrumentalities (Compl. ¶10).
Functionality and Market Context
- The complaint broadly alleges that the accused processors are used in "systems and methods of performing different accesses during a single RAS cycle to a memory array" (Compl. ¶10). The complaint does not provide any specific technical details regarding the operation of the i.MX53xD processors or their associated memory controllers. Similarly, the complaint does not provide sufficient detail for analysis of the product's market context or commercial importance.
IV. Analysis of Infringement Allegations
The complaint provides only high-level, conclusory allegations of infringement without reference to specific claim elements or product features. No probative visual evidence provided in complaint. The following tables summarize the infringement theory as can be inferred from the complaint's general allegations applied to the elements of representative independent claims.
’932 Patent Infringement Allegations (Claim 1)
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an array of rows and columns of memory cells; | The complaint alleges that the accused processors are used in systems with a memory array. | ¶10 | col. 9:2-3 |
| row decoder circuitry for selecting a said row in said array for access; | The complaint alleges the accused processors are used in systems that perform accesses to a memory array, which would require row selection. | ¶10 | col. 9:4-5 |
| first column decoder circuitry for selecting a location within a first group of said columns along said selected row; | The complaint alleges the accused processors are used in systems that perform accesses to a memory array, which would require column selection. | ¶10 | col. 9:6-8 |
| second column decoder circuitry for selecting for access a location within a second group of said columns along said selected row; and | The complaint alleges the accused processors are used in systems that perform accesses to a memory array, which would require column selection for a second group. | ¶10 | col. 9:10-12 |
| control circuitry operable during a selected random cycle to initiate a page access... and a random access... | The complaint alleges the accused processors are used in systems performing "different accesses during a single RAS cycle." | ¶10 | col. 9:13-18 |
’932 Patent Infringement Allegations (Claim 12)
| Claim Element (from Independent Claim 12) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an array of rows and columns of memory cells; | The complaint alleges that the accused processors are used in systems with a memory array. | ¶10 | col. 10:13-14 |
| row decoder circuitry for selecting in response to a row address a row in said array for access; | The complaint alleges the accused processors are used in systems that perform accesses to a memory array, which would require row selection. | ¶10 | col. 10:15-16 |
| column decoder circuitry for selecting at least one location within a first group of columns...; and | The complaint alleges the accused processors are used in systems that perform accesses to a memory array, which would require column selection. | ¶10 | col. 10:17-20 |
| at least one shift register for providing serial access to ones of said cells within a second group of columns along said selected row. | The complaint alleges the accused processors are used in systems performing "different accesses," which could include serial access. | ¶10 | col. 10:21-24 |
Identified Points of Contention
- Evidentiary Questions: The complaint lacks specific factual allegations linking the accused processors to the claimed invention. A central issue will be whether the plaintiff can substantiate its claims with evidence showing that the i.MX53xD processors, or systems using them, actually implement the specific architectures and methods of the '932 patent.
- Technical Questions: A key technical question is whether the memory controllers associated with the i.MX53xD processors implement the claimed column-grouping architecture. For infringement of Claim 12, for example, the analysis will question whether the accused systems contain a "shift register" for "serial access" to a "second group of columns" that operates distinctly from the "column decoder circuitry" for a "first group of columns."
- Scope Questions: The analysis may turn on the scope of functional language. For Claim 1, a question is whether the accused device's memory protocol performs the specific sequence of initiating a "page access" during what the patent defines as a "random cycle." The complaint does not provide the detail needed to evaluate this.
V. Key Claim Terms for Construction
The complaint's lack of detail prevents the identification of terms already in dispute. However, the following terms are fundamental to the patent's claims and their construction will likely be critical.
The Term: "control circuitry operable during a selected random cycle to initiate a page access" (Claim 1)
- Context and Importance: This term defines the core functionality of Claim 1, which requires mixing two specific access types (random and page) within a particular sequence. Infringement will depend on whether the accused device's memory controller is found to operate in this specific manner.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party may argue the claim language should be read functionally to cover any controller that can switch from a random to a page access within a single RAS period, pointing to the general description of the timing diagram in Figure 3 as an example of this capability (e.g., ’932 Patent, col. 8:10-24).
- Evidence for a Narrower Interpretation: A party may argue the term is limited by the patent's specific embodiment, which uses dedicated mode select pins (MODE SEL0, MODE SEL1) to dynamically switch between access types as shown in the table at column 8 (’932 Patent, col. 8:1–9).
The Term: "at least one shift register for providing serial access to ones of said cells within a second group of columns" (Claim 12)
- Context and Importance: This structural element is central to Claim 12 and distinguishes the claimed invention from memories that only provide parallel access. The presence and function of a corresponding structure in accused systems will be a key point of infringement analysis.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes the function of the shift register as enabling a "serial data stream" (’932 Patent, col. 6:28–31), which could support an interpretation covering any hardware that serially outputs data from a selected group of memory cells, even if not a traditional shift register.
- Evidence for a Narrower Interpretation: The patent’s diagrams depict the shift registers (207) as distinct components coupled to a specific "Group III" of columns (’932 Patent, Fig. 2). This could support a narrower construction requiring a physically or logically distinct hardware block dedicated to serial access for a dedicated group of columns.
VI. Other Allegations
Indirect Infringement
- The complaint makes no allegations of indirect infringement (inducement or contributory infringement), pleading only direct infringement under 35 U.S.C. § 271(a) (Compl. ¶10).
Willful Infringement
- The complaint does not allege willful infringement. While the prayer for relief requests a declaration that the case is "exceptional" under 35 U.S.C. § 285, the complaint body contains no factual allegations, such as pre-suit knowledge of the patent, that would typically support a claim for willfulness or an exceptional case finding (Compl., Prayer for Relief ¶C).
VII. Analyst’s Conclusion: Key Questions for the Case
The resolution of this case will likely depend on the answers to a few central questions, which are primarily evidentiary and technical due to the complaint's lack of specificity.
- A central evidentiary issue is substantiation: Can the plaintiff, through discovery, produce technical documentation, source code, or expert analysis sufficient to demonstrate that the accused i.MX53xD processors or their associated memory systems practice the specific methods and structures of the asserted claims? The complaint, as filed, presents no such evidence.
- A core question will be one of architectural correspondence: Do the memory systems that interface with the accused processors actually implement the claimed architecture of partitioned column groups, where different groups are managed by distinct access hardware (e.g., column decoders for a "first group" and shift registers for a "second group")?
- A key technical question will be one of operational mode: Does the accused system's memory controller operate in the precise manner claimed, for instance by initiating a page access within a random access cycle (per Claim 1) or by facilitating simultaneous serial and parallel-decoded accesses to different column groups within a single RAS cycle (per Claim 12 and its dependent claims)?