North Star Innovations Inc v. Hewlett Packard Co

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: North Star Innovations Inc. (Delaware)
  • Defendant: Hewlett-Packard Company (Delaware)
  • Plaintiff’s Counsel: Farnan LLP; Flachsbart & Greenspoon, LLC
• Case Identification: 1:16-cv-00728, D. Del., 08/19/2016
• Venue Allegations: Plaintiff alleges venue is proper in the District of Delaware because Defendant has transacted business in the state, including making, using, selling, and distributing products there.
• Core Dispute: Plaintiff alleges that Defendant’s HP ElitePad tablet, which contains synchronous memory devices, infringes a patent related to a method for observing the internal mode of a memory device.
• Technical Context: The technology concerns methods for testing and debugging synchronous dynamic random access memory (SDRAM), a critical component in modern computing devices, by making its internal configuration state externally observable.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,892,777 - "Apparatus and Method for Observing the Mode of a Memory Device"

• Issued: April 6, 1999

The Invention Explained

• Problem Addressed: The patent addresses the increasing difficulty of testing complex memory devices like SDRAMs. As these devices operate based on an internal "state machine" configured by a "mode register," it is difficult for testers to know the device's current state, especially in embedded systems where direct access to memory pins is limited (’777 Patent, col. 1:38-51). This makes it hard to predict output, validate operation, or debug an invalid state (’777 Patent, col. 1:40-45).
• The Patented Solution: The invention provides a method and circuit to read the contents of the internal mode register and output this value onto existing output pins (such as address or data pins). This is done at a time when no conventional data output from the memory array is expected, such as during a power-down or other specific test mode (’777 Patent, Abstract; col. 5:1-14). Figure 3 illustrates this concept, showing a multiplexer (306) that selects between the conventional data path from the memory array (302) and the mode register value (MROUT) to send to the output pins.
• Technical Importance: This approach provides observability into the internal configuration of an SDRAM using minimal additional circuitry, which "substantially eases the burden of testing a data processing system" incorporating such a device (’777 Patent, col. 2:26-31).

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 1 (Compl. ¶8, ¶10).
• The essential elements of independent claim 1 are:
  • storing a received value in the control register responsive to a first signal;
  • outputting the received value responsive to a second control signal when no output is expected from the memory device; and
  • disabling the operation of the memory device responsive to the second control signal subsequent to the step of outputting.
• The complaint states that Defendant infringes "one or more claims" of the patent, suggesting the right to assert other claims may be reserved (Compl. ¶5).

III. The Accused Instrumentality

Product Identification

• The complaint names the "HP ElitePad 1000 G2 Tablet (64GB)" as the exemplary infringing product (Compl. ¶8).

Functionality and Market Context

• The infringement allegations focus on the tablet's memory subsystem, which includes LPDDR3 SDRAM that conforms to the JEDEC industry standard (Compl. ¶11). The complaint alleges that the tablet performs the infringing method through the operation of its Elpida LPDDR3 SDRAM (Part#: FA164A2MA-GD-F) in communication with its Intel Atom processor (Part#: Z3795) (Compl. ¶12, ¶3). A board photo in the complaint identifies these specific components, showing the Elpida SDRAM and Intel processor on the tablet's mainboard (Compl. p. 3). The allegedly infringing functionality involves using a standard JEDEC command, the Mode Register Read (MRR) command, to read the status of an on-chip temperature sensor, which is stored in a specific mode register (MR4) (Compl. ¶11, ¶13, ¶14).

IV. Analysis of Infringement Allegations

5,892,777 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: The dispute may center on whether a standard operational feature of LPDDR3 memory (reading a temperature sensor) falls within the scope of a claim that, based on the patent's embodiments, appears to describe a dedicated test or debug mode (e.g., POWERDOWN mode). A central question is whether the claim phrase "when no output is expected from the memory device" is limited to such a test mode or broadly covers any time the main memory array is not being accessed.
• Technical Questions: A key technical question is whether the accused functionality constitutes "disabling the operation of the memory device." The complaint alleges that temporarily supporting only a "no operation" command during a specific read cycle meets this limitation (Compl. ¶21). This may be contrasted with the patent's embodiment, which describes disabling the device during a "POWERDOWN mode" (’777 Patent, col. 4:36–37), raising the question of whether a temporary command restriction is equivalent to disabling the device's operation.

V. Key Claim Terms for Construction

• The Term: "disabling the operation of the memory device"

  • Context and Importance: The interpretation of this term is critical to determining if the accused functionality—which allegedly supports only a "no operation" command during a Mode Register Read—meets the claim limitation. Practitioners may focus on whether this requires a complete shutdown of the device or merely a temporary suspension of other commands.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not specify the degree or duration of the "disabling," which may support an argument that any temporary prevention of other operations suffices.
    • Evidence for a Narrower Interpretation: The specification's primary embodiment links this concept to a "POWERDOWN mode," in which "the memory device 200 is disabled" (’777 Patent, col. 4:36-37). This could support an argument that the term requires a more comprehensive deactivation of the device, rather than just a momentary command restriction.

• The Term: "when no output is expected from the memory device"

  • Context and Importance: This phrase defines the condition under which the mode register value can be outputted. Its scope will determine whether the accused Mode Register Read command, a standard operational command, can be considered infringing.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The plain language could be argued to cover any clock cycle where a data read from the main memory array is not scheduled, which would include the timing of the accused MRR command.
    • Evidence for a Narrower Interpretation: The specification repeatedly links the outputting of the mode register to a "POWERDOWN mode," a state where the device is disabled and thus would not be expected to produce any output (’777 Patent, col. 4:46-50, col. 5:4-9). This suggests the phrase may be tied to a specific non-operational or test state, not just any idle moment during normal operation.

VI. Other Allegations

• Indirect Infringement: The prayer for relief seeks an injunction against "inducement and contributory infringement" (Compl. p. 8, ¶D), but the body of the complaint does not set forth specific factual allegations to support the knowledge or intent elements required for such claims.
• Willful Infringement: The complaint does not allege pre-suit knowledge of the ’777 Patent. The prayer for relief requests a finding that the case is "exceptional" under 35 U.S.C. § 285 (Compl. p. 8, ¶C), which is often associated with willfulness, but the complaint lacks specific factual pleadings to support this allegation.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case may depend on the court's interpretation of several key technical and legal issues. The central questions for the court appear to be:

• A primary issue will be one of claim scope: can the phrase "disabling the operation of the memory device," as described in the context of a "POWERDOWN" mode in the patent's embodiment, be construed to cover the accused functionality, where the memory device temporarily supports only a "no operation" command during a standard read cycle?
• A second core issue will be one of definitional interpretation: does the condition "when no output is expected from the memory device" refer broadly to any clock cycle where the main memory array is idle, or is it limited to a specific, non-operational test state as depicted in the patent's specification?
• Ultimately, the case raises a fundamental question of technical equivalence: does a routine operational feature of a modern, standardized memory component (reading an internal sensor via a standard command) infringe claims directed at what appears to be a dedicated method for testing and debugging a memory device's overall configuration state?