Smart Semiconductor LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Smart Semiconductor, LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff’s Counsel: Devlin Law Firm LLC
• Case Identification: 1:17-cv-00457, D. Del., 04/21/2017
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is incorporated in Delaware, conducts regular business in the district, and the alleged acts of infringement occur within the district.
• Core Dispute: Plaintiff alleges that certain of Defendant’s Core i3, i5, and i7 microprocessors infringe three patents related to specialized circuits that reduce the "lock-in" time for phase-locked loops.
• Technical Context: Phase-locked loops (PLLs) are fundamental circuit blocks used for frequency synthesis and clock synchronization in high-speed digital electronics, including microprocessors.
• Key Procedural History: The complaint does not reference any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,242,254 - “Adjustable Lock-In Circuit for Phase-Locked Loops”, Issued July 10, 2007

The Invention Explained

• Problem Addressed: The patent describes conventional phase-locked loops (PLLs) as suffering from slow "lock-in time," the time required for the loop to stabilize and synchronize. This inefficiency consumes unnecessary time and power, presenting a "serious bottleneck" in the design and operation of integrated circuits. (’254 Patent, col. 1:58-64; col. 2:1-4).
• The Patented Solution: The invention proposes an "adjustable lock-in circuit" that establishes an initial voltage condition closer to the final locked state, thereby reducing lock-in time. It achieves this using a sensor that compares a feedback voltage from the PLL's filter with an adjustable, external "reference voltage." Based on this comparison, the circuit provides a corrective current to rapidly drive the filter voltage toward the desired level. (’254 Patent, Abstract; col. 2:43-49).
• Technical Importance: This approach allows for a "targeted lock-in time," aiming to drastically improve system startup speed and reduce power consumption in complex electronics. (’254 Patent, col. 2:25-33).

Key Claims at a Glance

• The complaint asserts independent claim 1. (Compl. ¶11).
• Claim 1 requires:
  • An adjustable lock-in circuit for enabling any phase-locked loop to become locked according to a targeted lock-in time.
  • A feedback line connected to the circuit's output and a filter's output.
  • A sensor for comparing a feedback voltage with a reference voltage and providing an output.
  • Two stacked PMOS transistors connected between a power supply and the output.
  • Two stacked NMOS transistors connected between the output and ground.
• The complaint also asserts dependent claims 8, 9, 10, 14, 18, and 19. (Compl. ¶11).

U.S. Patent No. 7,224,233 - “Smart Lock-In Circuit for Phase-Locked Loops”, Issued May 29, 2007

The Invention Explained

• Problem Addressed: Like the ’254 Patent, this patent targets the slow locking and high power consumption inherent in conventional PLL designs. (’233 Patent, col. 1:58-62).
• The Patented Solution: This invention discloses a "smart lock-in circuit" that uses a sensor to compare the PLL's filter voltage against a "midpoint voltage." Critically, this midpoint voltage is not an external reference but is an intrinsic property determined by the physical "device aspect ratios of the sensor" itself. If the filter voltage differs from this intrinsic midpoint, the circuit injects current to quickly drive the voltage toward the target, establishing an initial condition that accelerates locking. (’233 Patent, Abstract; col. 4:9-22).
• Technical Importance: By relying on an intrinsic, design-imparted midpoint voltage, this solution seeks to achieve fast locking in a highly efficient and cost-effective manner, avoiding the complexity of other fast-locking schemes. (’233 Patent, col. 2:25-33).

Key Claims at a Glance

• The complaint asserts independent claim 1. (Compl. ¶30).
• Claim 1 requires:
  • A smart lock-in circuit for enabling any phase-locked loop to become locked according to schedule.
  • A feedback line connected to the circuit's output and a filter's output.
  • A sensor for sensing a voltage at the filter output, comparing it with a midpoint voltage decided by the sensor's device aspect ratios, and providing a response.
  • Two stacked PMOS transistors connected between a power supply and the output.
  • Two stacked NMOS transistors connected between the output and ground.
• The complaint also asserts dependent claims 2, 4, 6, 12, 15, and 19. (Compl. ¶30).

U.S. Patent No. 7,515,003 - “Filter-Based Lock-In Circuits for PLL and Fast System Startup”, Issued April 7, 2009

• Technology Synopsis: This patent discloses a lock-in circuit designed to reduce system startup time and latency. The circuit is centered on an upper and lower transistor pair forming a "single bidirectional node." A "sensing inverter" compares the voltage at this node to its own intrinsic input transition voltage, allowing the circuit to rapidly set an initial voltage condition that is "almost the same" as the target, thereby speeding up system initialization. (’003 Patent, Abstract; col. 8:44-62).
• Asserted Claims: The complaint asserts independent claim 1 and dependent claims 2, 6, 11, 15, and 20. (Compl. ¶49).
• Accused Features: Infringement is alleged based on the accused processors purportedly comprising a filter-based lock-in circuit with an upper PMOS and lower NMOS transistor forming a single bidirectional node, a sensing inverter, and a logic gate. (Compl. ¶51).

III. The Accused Instrumentality

• Product Identification: The accused instrumentalities are a range of Intel Core™ i3, i5, and i7 processors, identified by various part numbers (e.g., i7-67xx, i5-7Y54, i3-63xx). (Compl. ¶11, ¶30, ¶49).
• Functionality and Market Context: The complaint alleges, upon information and belief, that these processors incorporate the patented lock-in circuits within their internal PLLs. (Compl. ¶13, ¶32, ¶51). The alleged function of this circuitry is to achieve a "substantial increase in acquisition time compared to phase-locked loops using conventional charge pump configurations." (Compl. ¶13, ¶32, ¶51). The complaint notes that Defendant sells these products throughout the United States. (Compl. ¶3). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’254 Patent Infringement Allegations

• Identified Points of Contention:
  • Technical Question: The complaint's allegations are based on "information and belief" and cite the "presence" of certain components. A primary question will be what evidence Plaintiff can produce to demonstrate that the accused processors contain a circuit that functions as the claimed "sensor" by performing a comparison between a "feedback voltage" and a "reference voltage."
  • Scope Question: The infringement analysis may focus on whether the term "sensor," as described in the patent (e.g., an operational amplifier or comparator), reads on the specific circuitry implemented in the accused processors.

’233 Patent Infringement Allegations

• Identified Points of Contention:
  • Technical Question: The central technical dispute will likely concern the "midpoint voltage" limitation. The key question is whether Plaintiff can show that the accused circuits operate by comparing a sensed voltage to an intrinsic midpoint voltage that is specifically "decided by device aspect ratios of the sensor," a highly specific physical and functional characteristic.
  • Evidentiary Question: The complaint does not provide reverse-engineering reports or other technical evidence to support its conclusory allegations. The case will depend on what facts are revealed in discovery about the actual design and operation of the accused processors' internal circuits.

V. Key Claim Terms for Construction

For the ’254 Patent

• The Term: "reference voltage"
• Context and Importance: This term is central to the claimed invention's "adjustable" nature. Proving infringement requires showing the accused circuit compares its feedback voltage against such a "reference voltage." Practitioners may focus on this term because its definition will determine whether an intrinsic or internally generated voltage in the accused device can satisfy the claim, or if an externally supplied or explicitly programmable voltage is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term is not explicitly defined, potentially allowing for a functional interpretation covering any voltage used as a benchmark for comparison.
  • Evidence for a Narrower Interpretation: The specification discusses the reference voltage in the context of being "programmable" and based on "selecting taps of a segmented resistor string," suggesting it is a deliberately set, adjustable value, not a fixed internal property. (’254 Patent, col. 8:5-15; Claim 18).

For the ’233 Patent

• The Term: "midpoint voltage decided by device aspect ratios of the sensor"
• Context and Importance: This phrase defines the core technical distinction of the ’233 patent—the use of an intrinsic, physically determined voltage for comparison rather than an external reference. The entire infringement case for this patent hinges on proving that the accused Intel circuits employ this specific mechanism.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the midpoint functionally as the voltage where "the input voltage and the output voltage of the inverter are equal." (’233 Patent, col. 5:16-19). Plaintiff may argue any circuit achieving this state meets the limitation.
  • Evidence for a Narrower Interpretation: The specification provides a specific mathematical formula for the midpoint voltage based on transistor characteristics (e.g., carrier mobility, oxide capacitance, aspect ratio W/L). (’233 Patent, col. 5:20-25). Defendant may argue this formula limits the claim's scope to sensors that operate according to this precise physical principle.

VI. Other Allegations

• Indirect Infringement: The complaint includes allegations that Defendant infringes by "providing and causing to be used" the accused processors, which suggests a claim for induced infringement. (Compl. ¶11, ¶30, ¶49). The complaint does not, however, plead specific facts to support the element of intent, such as referencing user manuals or technical documentation that instruct customers to use the processors in an infringing manner.
• Willful Infringement: The complaint does not contain an explicit allegation of willful infringement. However, the prayer for relief requests a "declaration that this case is exceptional under 35 U.S.C. § 285," which is the statutory basis for awarding enhanced damages and attorneys' fees, often in cases of willful or egregious infringement. (Compl. p. 14).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue for all asserted patents will be evidentiary sufficiency: The complaint is filed on "information and belief" and lacks specific factual support, such as reverse-engineered circuit diagrams, to substantiate its claims. A primary question for the court will be whether Plaintiff can produce, through discovery, concrete evidence demonstrating that the internal architecture of Intel's processors practices the specific functions and structures recited in the patent claims.
• The case will also turn on a question of technical scope: Can the functional claim language, such as the ’254 patent’s "sensor for comparing a feedback voltage with a reference voltage," be construed to read on the complex, integrated circuitry within the accused processors?
• Finally, for the ’233 patent, a key question will be one of operational principle: Does the accused processors' circuitry function based on a comparison to a "midpoint voltage decided by device aspect ratios," or does it operate on a different technical principle, creating a fundamental mismatch with the patent's core inventive concept?