DCT
1:17-cv-00459
Smart Semiconductor, LLC v Qualcomm Incorporated,
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Smart Semiconductor, LLC (Delaware)
- Defendant: Qualcomm Incorporated (Delaware); Qualcomm Technologies, Inc. (Delaware)
- Plaintiff’s Counsel: DEVLIN LAW FIRM LLC
- Case Identification: 1:17-cv-00459, D. Del., 04/21/2017
- Venue Allegations: Venue is asserted based on Defendants being Delaware corporations, conducting business in the district, and committing alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that a wide range of Defendant’s Snapdragon processors infringe three patents related to specialized circuits that reduce the lock-in time of phase-locked loops (PLLs).
- Technical Context: The technology concerns phase-locked loops, which are fundamental building blocks in modern semiconductors for generating stable, high-frequency clock signals required for processors in devices like smartphones.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2005-01-15 | U.S. Patent No. 7,224,233 Priority Date |
| 2005-04-08 | U.S. Patent No. 7,242,254 Priority Date |
| 2007-05-29 | U.S. Patent No. 7,224,233 Issued |
| 2007-05-30 | U.S. Patent No. 7,515,003 Priority Date |
| 2007-07-10 | U.S. Patent No. 7,242,254 Issued |
| 2009-04-07 | U.S. Patent No. 7,515,003 Issued |
| 2017-04-21 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,242,254 - Adjustable Lock-In Circuit for Phase-Locked Loops (Issued Jul. 10, 2007)
The Invention Explained
- Problem Addressed: The patent’s background section states that conventional phase-locked loops (PLLs) suffer from "slow locking and harmonic locking," and that existing "fast-locking" solutions are often "costly, complicated, and inefficient to implement" on integrated circuits (U.S. Patent No. 7,242,254, col. 1:56-62, 2:10-18).
- The Patented Solution: The invention proposes an "adjustable lock-in circuit" that works alongside a standard PLL. This circuit uses a sensor to compare a feedback voltage from the PLL's filter with a programmable reference voltage. If the feedback voltage has not reached the reference level, the circuit injects or sinks current to rapidly drive the filter voltage towards that reference, thereby establishing an initial loop condition that is much closer to the final locked state and reducing the overall time needed to achieve a stable lock (’254 Patent, Abstract; col. 2:35-52).
- Technical Importance: The technology aims to provide a "highly cost-effective fast-locking phase-locked loop" with significant improvements in lock-in time, performance, cost, and power consumption, which are critical metrics for complex system-on-chip (SoC) designs (’254 Patent, col. 2:24-32).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶12).
- Claim 1 of the ’254 Patent recites:
- An adjustable lock-in circuit for enabling any phase-locked loop to become locked according to a targeted lock-in time, comprising:
- a feedback line connected with the output of the adjustable lock-in circuit and also coupled to the output of a filter;
- a sensor for comparing a feedback voltage with a reference voltage and providing its output;
- two stacked PMOS transistors connected between power supply and the output; and
- two stacked NMOS transistors connected between the output and ground.
- The complaint reserves the right to assert dependent claims 8, 9, 10, 14, 18, and 19 (Compl. ¶12).
U.S. Patent No. 7,224,233 - Smart Lock-In Circuit for Phase-Locked Loops (Issued May 29, 2007)
The Invention Explained
- Problem Addressed: Similar to the ’254 Patent, this patent addresses the slow lock-in times of conventional PLLs and the complexity of existing fast-locking solutions (U.S. Patent No. 7,224,233, col. 1:57-2:24).
- The Patented Solution: This patent describes a "smart lock-in circuit" that uses a sensor to compare the PLL's filter voltage against a "midpoint voltage" that is intrinsically determined by the physical "device aspect ratios of the sensor" itself, rather than an external reference. If a discrepancy exists, the circuit turns on transistors to inject current, rapidly driving the filter voltage to this internal midpoint and significantly accelerating the locking process (’233 Patent, Abstract; col. 4:8-21).
- Technical Importance: This design seeks to provide a fast-locking capability that is highly efficient to implement on-chip, offering improvements in performance, cost, and design time by using the inherent physical characteristics of the sensor to set the target voltage (’233 Patent, col. 2:25-34).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶31).
- Claim 1 of the ’233 Patent recites:
- A smart lock-in circuit for enabling any phase-locked loop including at least a filter to become locked according to schedule, comprising:
- a feedback line connected to an output and input of the smart lock-in circuit and also coupled to an output of a filter;
- a sensor for sensing a voltage at the filter output, comparing with a midpoint voltage decided by device aspect ratios of the sensor, and providing its response;
- two stacked PMOS transistors connected between power supply and the output; and
- two stacked NMOS transistors connected between the output and ground.
- The complaint reserves the right to assert dependent claims 2, 4, 6, 12, 15, and 19 (Compl. ¶31).
Multi-Patent Capsule
- Patent Identification: U.S. Patent No. 7,515,003, "Filter-Based Lock-In Circuits for PLL and Fast System Startup," issued April 7, 2009.
- Technology Synopsis: This patent addresses slow system startup times in electronic devices, which it attributes to the slow lock-in performance of PLLs (U.S. Patent No. 7,515,003, col. 3:5-13). The invention is a "filter-based lock-in circuit" that uses a sensing inverter to compare the voltage at a shared "single bidirectional node" to the inverter's own inherent input transition voltage, thereby quickly initializing the PLL filter voltage to a near-optimal state to reduce overall system startup time (’003 Patent, Abstract).
- Asserted Claims: Independent claim 1 (Compl. ¶50).
- Accused Features: The complaint alleges that the accused Snapdragon processors contain filter-based lock-in circuits that reduce system startup time and embody the elements of claim 1 (Compl. ¶52).
III. The Accused Instrumentality
- Product Identification: The complaint names an extensive list of Qualcomm processors as the "Infringing Instrumentalities," including but not limited to the Snapdragon 808, 810, 820, 821, 835, X50, 805, and various S3 and S4 models (Compl. ¶¶12, 31, 50).
- Functionality and Market Context: The complaint alleges, upon information and belief, that these processors incorporate circuits that provide for a "substantial increase in acquisition time compared to phase-locked loops using conventional charge pump configurations" (Compl. ¶¶14, 33, 52). These processors are foundational components in a vast range of consumer electronics, particularly cellular phones (Compl. ¶¶58, 60).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
U.S. Patent No. 7,242,254 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a feedback line connected with the output of the adjustable lock-in circuit and also coupled to the output of a filter | The complaint alleges on information and belief that the accused products contain a feedback line connected to the output of the adjustable lock-in circuit and a filter. | ¶14 | col. 3:65-4:2 |
| a sensor for comparing a feedback voltage with a reference voltage and providing its output | The complaint alleges on information and belief that the accused products comprise a circuit with a sensor that compares a feedback voltage with a reference voltage and provides an output. | ¶14 | col. 2:42-45 |
| two stacked PMOS transistors connected between power supply and the output | The complaint alleges the presence of two stacked PMOS transistors in the accused products. | ¶14 | col. 4:4-5 |
| two stacked NMOS transistors connected between the output and ground | The complaint alleges the presence of two stacked NMOS transistors in the accused products. | ¶14 | col. 4:6-7 |
U.S. Patent No. 7,224,233 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a feedback line connected to an output and input of the smart lock-in circuit and also coupled to an output of a filter | The complaint alleges on information and belief that the accused products contain a feedback line. | ¶33 | col. 4:3-4 |
| a sensor for sensing a voltage at the filter output, comparing with a midpoint voltage decided by device aspect ratios of the sensor, and providing its response | The complaint alleges on information and belief that the accused products' circuit includes a sensor for sensing a voltage, comparing it with a midpoint voltage that is decided by the sensor's device aspect ratios, and providing a response. | ¶33 | col. 2:41-45 |
| two stacked PMOS transistors connected between power supply and the output | The complaint alleges the presence of two stacked PMOS transistors in the accused products. | ¶33 | col. 4:4-5 |
| two stacked NMOS transistors connected between the output and ground | The complaint alleges the presence of two stacked NMOS transistors in the accused products. | ¶33 | col. 4:5-7 |
- Identified Points of Contention:
- Evidentiary Questions: The complaint's allegations are made "on information and belief" and are conclusory, tracking the claim language without providing specific technical details about the accused products' operation. A central point of contention will be whether Plaintiff can produce evidence from reverse engineering or discovery that substantiates these bare allegations for the highly complex accused processors.
- Scope Questions: The term "sensor" is central to both patents. The dispute may turn on whether a standard logic gate or inverter within the accused processors can be considered a "sensor" as claimed, or if the patents require a more specialized, distinct component.
- Technical Questions: For the ’233 Patent, a critical technical question is whether any accused circuit component actually uses a comparison voltage that is specifically "decided by device aspect ratios of the sensor," as this is a highly specific mechanism of operation. For the ’254 Patent, a similar question exists regarding whether the accused circuits use a "reference voltage" for comparison as required by the claims.
V. Key Claim Terms for Construction
For the ’254 Patent
- The Term: "a sensor for comparing a feedback voltage with a reference voltage"
- Context and Importance: This term defines the core functional element of claim 1. The viability of the infringement claim hinges on whether the accused products contain a structure that performs this specific comparison using a "reference voltage." Practitioners may focus on this term because the defendant could argue its circuits use an alternative mechanism, such as a fixed trip-point inverter, that does not rely on a "reference voltage."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent specification discloses that the "sensor" can be an "operational amplifier," an "amplifier with a reference voltage," or a "comparator with a reference voltage" (’254 Patent, claims 8-10). Further, the "reference voltage" is described as potentially programmable or selectable from a resistor string, suggesting flexibility in its implementation (’254 Patent, claims 17-18).
- Evidence for a Narrower Interpretation: The figures consistently depict the reference voltage (V_REFL, V_REFH) as a distinct input to the comparator circuits (e.g., ’254 Patent, Fig. 3, 302 & 304). A party could argue that this implies the "reference voltage" must be an externally supplied or separately generated signal, rather than a voltage level inherent to the "sensor" itself.
For the ’233 Patent
- The Term: "midpoint voltage decided by device aspect ratios of the sensor"
- Context and Importance: This limitation is the technical heart of the ’233 patent, distinguishing it from systems using external reference voltages. Infringement will require proof that the accused sensor's comparison threshold is determined by its physical layout (i.e., the width-to-length ratios of its transistors).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification explains how the midpoint voltage of a standard inverter is a function of its transistor properties, including the aspect ratios (’233 Patent, col. 5:16-24). A plaintiff might argue that any inverter-based sensing element inherently has a midpoint voltage "decided by" its aspect ratios.
- Evidence for a Narrower Interpretation: The summary of the invention and abstract emphasize that the time to reach the midpoint voltage "can be scaled by a device aspect ratio of the transistor," suggesting an intentional design choice rather than an incidental property (’233 Patent, Abstract; col. 2:48-51). A defendant could argue the term requires that the aspect ratios be specifically engineered to set a desired midpoint voltage for the lock-in function, not merely that they have some inherent trip point.
VI. Other Allegations
- Indirect Infringement: The complaint does not plead any counts for indirect infringement (i.e., induced or contributory infringement); it alleges only direct infringement under 35 U.S.C. § 271(a) (Compl. ¶¶12, 31, 50).
- Willful Infringement: The complaint does not explicitly allege willful infringement. It does, however, request a declaration that the case is "exceptional under 35 U.S.C. § 285," which is the basis for an award of attorneys' fees (Compl., Prayer for Relief ¶C). The complaint does not allege any facts to support pre-suit knowledge by the Defendants, a common basis for willfulness.
VII. Analyst’s Conclusion: Key Questions for the Case
The Evidentiary Hurdle: The central issue in the early stages of this case will be one of evidence. Can the Plaintiff, proceeding on "information and belief," develop sufficient factual support through discovery and technical analysis to show that the complex internal circuitry of the accused Snapdragon processors practices the specific limitations of the asserted claims? The complaint's lack of technical detail places a significant burden on the Plaintiff to substantiate its allegations.
The Mechanism of Operation: A key technical question will be one of functional correspondence. Do the accused Qualcomm circuits, which are designed to achieve fast clock-locking, operate by the specific mechanisms claimed in the patents—namely, comparing a filter voltage to either a programmable "reference voltage" (’254 patent) or an internal "midpoint voltage decided by device aspect ratios" (’233 patent)—or do they employ a different, non-infringing technical approach to achieve a similar outcome?
The Scope of "Sensor": The case may turn on a question of definitional scope during claim construction. Will the court construe the term "sensor" broadly to encompass standard logic components like inverters that have inherent voltage trip points, or will it require a more specialized structure designed explicitly for the comparison function described in the patents? The answer to this question could be dispositive for infringement.