DCT
1:17-cv-00554
Wi LAN Inc v. MStar Semiconductor Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Wi-LAN Inc. (Canada)
- Defendant: MediaTek, Inc. (Taiwan); MediaTek USA, Inc. (Delaware); MStar Semiconductor, Inc. (Taiwan)
- Plaintiff’s Counsel: Farnan LLP; Bragalone Conroy P.C.
- Case Identification: 1:17-cv-00554, D. Del., 05/11/2017
- Venue Allegations: Venue is asserted on the basis that Defendants are subject to personal jurisdiction in the District of Delaware, conduct business in the district, and have placed infringing products into the stream of commerce with the knowledge that they will be sold there. MediaTek USA, Inc. is a Delaware corporation.
- Core Dispute: Plaintiff alleges that Defendants' semiconductor chips, which feature a de-interlacing process, infringe a patent related to methods for displaying interlaced video on non-interlaced monitors.
- Technical Context: The technology concerns video signal processing, specifically converting legacy interlaced video signals (common in broadcasting) for display on modern progressive-scan monitors (like digital TVs and computer screens) without visual artifacts.
- Key Procedural History: The complaint alleges that Defendants were on notice of the patent-in-suit due to prior litigation filed by Plaintiff against Defendants' customers (e.g., Sharp, Vizio, Toshiba) beginning as early as 2012 and more directly in 2015. The complaint also notes that a petition for inter partes review of the patent-in-suit, filed by one of these customers, was denied institution by the Patent Trial and Appeal Board (PTAB). Public records indicate that claim 8 of the patent was disclaimed in 2016.
Case Timeline
| Date | Event |
|---|---|
| 1996-02-14 | '654 Patent Priority Date (Provisional Application) |
| 2002-03-19 | '654 Patent Issue Date |
| 2014-02-01 | MStar Semiconductor, Inc. merges with MediaTek, Inc. |
| 2015-05-11 | Notice alleged via lawsuit against Defendants' customers (Sharp, Vizio) |
| 2016-01-20 | Disclaimer of '654 Patent Claim 8 filed |
| 2016-04-01 | PTAB denies institution of IPR on '654 Patent (IPR2016-00010) |
| 2017-05-11 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,359,654 - “Methods and Systems for Displaying Interlaced Video on Non-Interlaced Monitors”
- Patent Identification: U.S. Patent No. 6,359,654, “Methods and Systems for Displaying Interlaced Video on Non-Interlaced Monitors,” issued March 19, 2002.
The Invention Explained
- Problem Addressed: The patent addresses the technical challenge of converting interlaced video, where each frame is split into two fields (odd and even lines) captured at slightly different times, for display on a non-interlaced (progressive scan) monitor. Prior methods resulted in visual artifacts; for example, merging the two fields could create a "zipper like appearance" along moving vertical edges, while displaying only one of the two fields would halve the vertical resolution and create motion "jerkiness" (’654 Patent, col. 1:55-63, col. 2:20-42).
- The Patented Solution: The invention proposes a method that displays both fields of an interlaced frame sequentially, but first "adjusts" one of the fields to correct for the inherent half-line vertical offset between the odd and even fields. This adjustment can be achieved either by shifting the display position of one field on the monitor or by altering the video data itself, for example through vertical interpolation between adjacent lines, before display (’654 Patent, Abstract; col. 5:6-19; Fig. 4).
- Technical Importance: The described method provided a way to maintain both the temporal smoothness (by using all fields) and the perceived vertical resolution of interlaced source material when shown on the increasingly prevalent non-interlaced displays, improving the viewing experience for content like broadcast television and film (’654 Patent, col. 1:11-15).
Key Claims at a Glance
- The complaint asserts infringement of at least claim 1 (Compl. ¶25).
- The essential elements of independent claim 1 are:
- capturing a first field and a second field of each pair of fields into respective buffers;
- scaling each of the first field and second field of each pair of fields to fill vertical resolution of the non-interlaced monitor;
- adjusting one of the first field or second field of the pair of fields to substantially correct for the vertical offset between the pairs of fields, where said adjusting is performed concurrently with said scaling;
- displaying the first field of each pair of fields on the non-interlaced monitor in a first time period; and
- displaying the second field of each pair of fields on the non-interlaced monitor in a second time period subsequent to the first time period.
- The complaint reserves the right to assert infringement of other claims of the ’654 patent (Compl. ¶24).
III. The Accused Instrumentality
Product Identification
- A broad range of MediaTek (MT) and MStar (MSD) branded semiconductor chips and chipsets, including but not limited to models MT5376, MT5380, MT5595, MSD95C, and MSD6308. The allegations extend to all similar models that implement Defendants' "MDDi de-interlacing process" (Compl. ¶18).
Functionality and Market Context
- The complaint alleges these chips are used in end products like digital televisions to process and display video signals (Compl. ¶19, ¶25). The accused functionality is the "MDDi de-interlace process," which is alleged to be a procedure for "displaying interlaced video data on a non-interlaced monitor" (Compl. ¶18, ¶25). Plaintiff alleges that incorporating this technology allows Defendants to "improve end product features" (Compl. ¶19).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
- Claim Chart Summary: The complaint outlines its infringement theory for claim 1 in narrative form. The core allegations are summarized below.
'654 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) capturing a first field and a second field of each pair of fields into respective buffers; | The accused products perform the step of "capturing a first field and a second field of each pair of fields into respective buffers." | ¶25 | col. 10:50-52 |
| (b) scaling each of the first field and second field of each pair of fields to fill vertical resolution of the non-interlaced monitor; | The accused products perform the step of "scaling each of the first field and second field of each pair of fields to fill vertical resolution of the non-interlaced monitor." | ¶25 | col. 10:53-56 |
| (c) adjusting one of the first field or second field of the pair of fields to substantially correct for the vertical offset..., where said adjusting is performed concurrently with said scaling; | The accused products perform the step of "adjusting one of the first field or second field of the pair of fields to substantially correct for the vertical offset between the pairs of fields, where said adjusting is performed concurrently with said scaling." | ¶25 | col. 10:57-61 |
| (d) displaying the first field of each pair of fields on the non-interlaced monitor in a first time period; and | When incorporated with a display device, the accused products perform the step of "displaying the first field of each pair of fields on the non-interlaced monitor for a first time period." | ¶25 | col. 10:62-64 |
| (e) displaying the second field of each pair of fields on the non-interlaced monitor in a second time period subsequent to the first time period. | When incorporated with a display device, the accused products perform the step of "displaying the second field of each pair of fields on the non-interlaced monitor in a second time period subsequent to the first time period." | ¶25 | col. 10:65-68 |
- Identified Points of Contention:
- Scope Questions: A central dispute may arise over the meaning of "concurrently with said scaling." The parties may contest whether this requires the adjusting and scaling operations to be performed in the same hardware step or merely as overlapping processes.
- Technical Questions: A key evidentiary question will be whether the accused "MDDi de-interlace process" actually performs the function of "adjusting... to substantially correct for the vertical offset" as required by the claim. The complaint alleges this functionality but does not provide specific technical details on how the accused chips achieve it (Compl. ¶25).
V. Key Claim Terms for Construction
The Term: "adjusting... to substantially correct for the vertical offset"
Context and Importance: This term captures the core novelty of the claimed invention. Its construction will be critical to determining infringement, as the outcome will depend on whether the accused MDDi process performs an operation that falls within the construed scope of this term.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes multiple distinct methods for achieving this correction, suggesting the term is not limited to a single implementation. It discloses both altering display position and modifying video data, stating "There are two ways presented to deal with the vertical offset" (’654 Patent, col. 5:12-19).
- Evidence for a Narrower Interpretation: A party might argue the scope should be tied more closely to the specific examples provided, such as repositioning by an integer number of display lines for certain scaling factors (’654 Patent, col. 5:30-35) or generating pixels by "averaging two vertically adjacent pixels from two lines" (’654 Patent, col. 6:14-16).
The Term: "concurrently with said scaling"
Context and Importance: Practitioners may focus on this term because the timing relationship between the "adjusting" and "scaling" steps is a specific limitation. Infringement will hinge on whether the accused products' architecture performs these two functions in a manner that can be described as "concurrent."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The flowchart in Figure 4 depicts "ADJUST" and "SCALE" as sequentially ordered but tightly linked steps, which a party could argue represents a concurrent or overlapping process rather than two wholly separate events in time. The patent abstract also links the two actions closely.
- Evidence for a Narrower Interpretation: The claim language recites adjusting "concurrently with said scaling," which could be argued to require simultaneous or near-simultaneous hardware operation, rather than a sequential process where one step follows another, however closely. The patent's description of adjusting "concurrent with the previous scaling step" in Figure 4 could be interpreted as a temporal, not merely logical, relationship.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement under 35 U.S.C. § 271(b), stating that Defendants take affirmative steps such as "creating advertisements," "making available instructions or manuals," and "developing infringing source code" to encourage infringement by third-party manufacturers and consumers (Compl. ¶¶28-29). The complaint also alleges contributory infringement under § 271(c), asserting the accused chips contain functionality that is a "material part" of the invention and not a "staple article[] of commerce suitable for substantial non-infringing use" (Compl. ¶30).
- Willful Infringement: Willfulness allegations are based on Defendants' alleged knowledge of the ’654 patent since at least May 11, 2015, stemming from prior lawsuits against their customers (Sharp, Vizio) and related indemnification requests and subpoenas (Compl. ¶27, ¶32). The complaint asserts that Defendants' continued infringement despite this notice has been "willful and intentional" (Compl. ¶32).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of claim construction and scope: how the court defines "adjusting... to substantially correct for the vertical offset" and "concurrently with said scaling." The viability of the infringement case will depend on whether the specific technical operations of Defendants' MDDi process are found to fall within the court's construction of these key limitations.
- A central evidentiary question will be one of technical proof: what evidence Plaintiff can produce to show that the accused chips, in operation, meet every limitation of the asserted claim. The dispute will likely move from the high-level allegations of the complaint to a granular, technical comparison of the accused chip's functionality against the patent's claims.