Invensas Corp v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Invensas Corporation (Delaware)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea); Samsung Austin Semiconductor, LLC (Delaware)
  • Plaintiff’s Counsel: Farnan LLP; Latham & Watkins LLP
• Case Identification: Invensas Corporation v. Samsung Electronics Co., Ltd., et al., 1:17-cv-01363, D. Del., 09/28/2017
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Samsung Austin Semiconductor, LLC is a Delaware corporation, and because Defendant Samsung Electronics Co., Ltd. is a foreign entity, for whom venue is proper in any judicial district.
• Core Dispute: Plaintiff alleges that Defendants’ Exynos processors, manufactured using advanced semiconductor fabrication techniques, infringe two patents related to methods and structures for achieving surface planarity during chemical-mechanical polishing.
• Technical Context: The technology addresses chemical-mechanical polishing (CMP), a fundamental process in modern semiconductor manufacturing used to create flat, uniform surfaces for the complex, multi-layered wiring (interconnects) within an integrated circuit.
• Key Procedural History: The complaint alleges that Plaintiff put Samsung on notice of the patents-in-suit and its alleged infringement as of April 20, 2016. The complaint also notes that Plaintiff has sued other Samsung affiliates on the same patents in a different judicial district. Post-dating the complaint, Inter Partes Review (IPR) proceedings were initiated against both patents. The provided patent documents include IPR certificates, issued in October 2023, which state that all asserted claims in this case (Claim 1 of the ’231 patent and Claim 16 of the ’946 patent) have been cancelled. This post-filing development raises a dispositive question about the ongoing viability of the asserted claims.

Case Timeline

Date	Event
1998-08-31	Priority Date for ’231 Patent and ’946 Patent
2001-05-15	Issue Date for U.S. Patent No. 6,232,231
2005-02-01	Issue Date for U.S. Patent No. 6,849,946
2016-04-20	Alleged date of first notice of infringement to Samsung
2017-09-28	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,232,231 - "Planarized Semiconductor Interconnect Topography and Method For Polishing a Metal Layer To Form Interconnect," issued May 15, 2001

The Invention Explained

• Problem Addressed: The patent’s background describes how conventional chemical-mechanical polishing (CMP) processes struggle to create a perfectly flat surface across a semiconductor wafer that has both wide features (like bond pads) and dense areas of narrow features (like interconnect lines). This can lead to undesirable effects like "dishing" (excessive material removal in wide areas) and "erosion," which compromise the circuit's performance and reliability (’231 Patent, col. 2:30-38; col. 3:1-43).
• The Patented Solution: The invention proposes a method to improve polishing uniformity by strategically adding non-functional "dummy trenches" into the dielectric layer in areas that would otherwise be empty, particularly between a wide trench and a series of narrow trenches (’231 Patent, Abstract). These dummy trenches are filled with conductive material along with the functional trenches. Their presence makes the overall pattern density more uniform, which helps the polishing pad apply even pressure across the wafer, thereby mitigating dishing and erosion and resulting in a "substantially planar" surface (’231 Patent, col. 5:26-44; Fig. 7).
• Technical Importance: This method provided a practical solution to a key manufacturing challenge, enabling more uniform planarization, which is critical for building reliable and high-performance multi-level integrated circuits (’231 Patent, col. 5:26-35).

Key Claims at a Glance

• The complaint asserts independent claim 1 (’231 Patent, col. 9:8-27; Compl. ¶15).
• The essential elements of Claim 1 include:
  • A method for providing a substantially planar semiconductor topography.
  • Etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first (wider) trench and a series of second (narrower) trenches.
  • Filling the dummy, first, and second trenches with a conductive material.
  • Polishing the conductive material to form dummy conductors exclusively in the dummy trenches and interconnects exclusively in the first and second trenches.
  • The resulting dummy conductors are electrically separate from underlying conductive features and are co-planar with the interconnect.
• The complaint reserves the right to assert other claims, including those dependent on claim 1 (Compl. ¶15).

U.S. Patent No. 6,849,946 - "Planarized Semiconductor Interconnect Topography and Method For Polishing a Metal Layer To Form Interconnect," issued February 1, 2005

The Invention Explained

• Problem Addressed: Like its parent ’231 patent, the ’946 patent addresses the problem of achieving global planarity in semiconductor manufacturing and avoiding defects like dishing and erosion that arise from non-uniform pattern density during CMP (’946 Patent, col. 2:35-44).
• The Patented Solution: While the ’231 patent claims the method, the ’946 patent claims the resulting physical structure or "topography." The invention is a semiconductor structure characterized by the presence of a wide trench, a series of narrow trenches, and a plurality of "dummy trenches" of a specific intermediate width situated between them (’946 Patent, col. 4:4-24). All these trenches contain conductive material, and the upper surfaces of the resulting "dummy conductors" and interconnects are "substantially coplanar," creating the desired flat surface (’946 Patent, Abstract; Fig. 7).
• Technical Importance: By claiming the resulting physical structure, the patent provides protection for the tangible output of the novel manufacturing process, complementing the method claims of the parent patent (’946 Patent, col. 4:40-50).

Key Claims at a Glance

• The complaint asserts independent claim 16 (’946 Patent, col. 10:16-41; Compl. ¶29).
• The essential elements of Claim 16 include:
  • A substantially planar semiconductor topography.
  • A plurality of laterally spaced dummy trenches located in a dielectric layer between a first (wide) trench and a series of second (narrow) trenches, with specific relative dimensional requirements.
  • Dummy conductors residing in the dummy trenches that are electrically separate from features below them.
  • Conductive lines in the first and second trenches, whose upper surfaces are substantially coplanar with the upper surfaces of the dummy conductors.
• The complaint reserves the right to assert other claims, including those dependent on claim 16 (Compl. ¶29).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Samsung's Exynos processors and other semiconductor chips, which are incorporated into products including, but not limited to, Samsung's Galaxy S6, S7, and S8 devices (Compl. ¶¶12, 15, 29).

Functionality and Market Context

The complaint alleges that the accused Exynos processors are manufactured using a process that creates structures infringing the patents-in-suit (Compl. ¶¶15-16). The relevant functionality is not end-user facing, but rather relates to the physical construction of the chip itself, specifically the use of varied-width trenches and dummy structures to achieve a planar interconnect topography (Compl. ¶¶18, 31). The complaint asserts these processors are used in Samsung’s flagship smartphones, positioning them as commercially significant products (Compl. ¶12). The complaint describes a cross-section of an accused Exynos processor as showing the first and second trenches having different widths (Compl. ¶20).

IV. Analysis of Infringement Allegations

’231 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein a lateral dimension of said first trench is greater than a lateral dimension of said second trenches	Samsung's process allegedly includes etching multiple dummy trenches into an insulating material between a wider "first interconnect" trench and narrower "second interconnect" trenches (Compl. ¶¶18-19).	¶¶18, 19	col. 7:4-24
filling said dummy trenches and said first and second trenches with a conductive material	The first, second, and dummy trenches in the accused processors are allegedly filled with a conductive material, such as copper (Compl. ¶20).	¶20	col. 7:25-39
polishing said conductive material to form dummy conductors exclusively in said dummy trenches and interconnect exclusively in said first and second trenches	Samsung's manufacturing process allegedly includes polishing the deposited conductive material until it is exclusively contained within the first, second, and dummy trenches (Compl. ¶21). The complaint describes a cross-section showing separate copper in the various trenches (Compl. ¶21).	¶21	col. 7:40-50
wherein said dummy conductors are electrically separate from said plurality of electrically conductive features and co-planar with said interconnect	The dummy conductors in the accused processors are alleged to be co-planar with the interconnects and electrically separate from the active or passive electrical components below them (Compl. ¶22).	¶22	col. 4:35-38

’946 Patent Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a plurality of laterally spaced dummy trenches in a dielectric layer, between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench and wherein...	The accused Exynos processors allegedly include multiple dummy trenches in an insulating layer located between a "first relatively wide trench" and a "series of second relatively narrow trenches" (Compl. ¶31). A cross-section is described as showing the required dimensional relationships between the trenches (Compl. ¶32).	¶¶31, 32	col. 7:4-13
dummy conductors in said laterally spaced dummy trenches and electrically separate from electrically conductive features below said dummy conductors	The accused processors allegedly contain copper-based dummy conductors in the dummy trenches that are electrically separate from underlying components and other conductive lines (Compl. ¶33).	¶33	col. 7:46-50
conductive lines in said series of second trenches and said first trench, wherein upper surfaces of said conductive lines are substantially coplanar with dummy conductor upper surfaces	The complaint alleges that a cross-section of the accused Exynos processors shows that the upper surfaces of the copper-based interconnects are substantially coplanar with the upper surfaces of the dummy conductors (Compl. ¶34).	¶34	col. 7:40-45

• Identified Points of Contention:
  • Process vs. Product Evidence: For the ’231 method patent, a key question is what evidence Plaintiff can obtain through discovery to prove Samsung’s internal manufacturing process performs the claimed steps, as opposed to simply inferring the process from the final product.
  • Structural Correspondence: For the ’946 patent, the dispute may center on whether the structures within Samsung's processors meet the specific dimensional and relational limitations of claim 16, such as the requirements that dummy trenches be "less than a lateral dimension of the first trench and greater than a lateral dimension of at least one of the series of second trenches."
  • Evidentiary Basis: The complaint’s allegations are made "on information and belief" and rely on descriptions of what "a cross section... shows" without providing the visual evidence itself (Compl. ¶¶17, 30). The case will depend on whether discovery validates these preliminary allegations with detailed technical evidence.

V. Key Claim Terms for Construction

• The Term: "dummy trenches" / "dummy conductors"

• Context and Importance: This is the central inventive concept. The definition will determine whether the structures used by Samsung for process uniformity (if any) are covered by the claims. The dispute may turn on whether the term is limited to structures with no electrical function whatsoever, or if it can read on structures that provide some ancillary electrical role (e.g., power/ground bussing) while primarily serving to aid planarization.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification suggests a functional definition, stating the dummy conductors "preferably serve no purpose except to improve the planarization of the interconnect level" (’231 Patent, col. 4:38-40), which could be argued to cover any feature primarily added for that purpose.
  • Evidence for a Narrower Interpretation: The claims require the dummy conductors to be "electrically separate from said plurality of electrically conductive features" (’231 Patent, col. 9:24-25). The specification also notes that the dummy conductors are "not connected to any active or passive device" (’231 Patent, col. 8:4-5), which could be used to argue for a narrower construction limited to electrically isolated structures.

• The Term: "substantially planar" / "substantially coplanar"

• Context and Importance: These are terms of degree that are critical to the infringement analysis. The entire purpose of the invention is to achieve a superior level of planarity. The parties will likely dispute the threshold of planarity required to meet this limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term could be construed according to its plain and ordinary meaning to one of skill in the art, which may allow for minor, commercially acceptable variations in height.
  • Evidence for a Narrower Interpretation: This term could be defined in relation to the prior art problems the patent sought to solve. The patent contrasts its resulting flat surface (Fig. 7) with the "dishing" and "recessed area" of the prior art (Fig. 4), suggesting "substantially planar" means the absence of such specific defects (’231 Patent, col. 3:1-7; col. 6:62-65).

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement, stating that Samsung encourages infringement by others (e.g., customers, other Samsung entities) through marketing materials, technical specifications, data sheets, and its sales and distribution channels for the accused processors (Compl. ¶¶26, 38).
• Willful Infringement: The willfulness claim is based on alleged pre-suit knowledge. The complaint alleges that Invensas notified Samsung of the patents and its infringing activities on "at least April 20, 2016," and that Samsung’s infringement continued despite this knowledge (Compl. ¶¶24-25, 36-37).

VII. Analyst’s Conclusion: Key Questions for the Case

• A threshold, and likely dispositive, question is one of claim viability: given that the asserted independent claims (Claim 1 of the ’231 patent and Claim 16 of the ’946 patent) were cancelled in post-filing IPR proceedings, as reflected in the provided patent documents, what legal basis, if any, remains for the complaint to proceed on these specific claims?
• A central technical question would be one of structural and dimensional correspondence: assuming the claims were valid, do the features within Samsung’s modern Exynos processors—designed for advanced fabrication nodes—meet the specific geometric and relational definitions recited in the 1998-priority-date claims, particularly for terms like "dummy trench" and the relative sizing of the various interconnects?
• An essential evidentiary question for the method patent (’231) would be one of process proof: what direct evidence can be marshaled from Samsung’s proprietary fabrication process to demonstrate that it literally performs the claimed sequence of "etching," "filling," and "polishing," rather than merely producing a structure from which those steps might be inferred?