DCT

1:17-cv-01863

ZiiLabs v. NVIDIA Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:17-cv-01863, D. Del., 12/27/2017
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is a Delaware corporation.
  • Core Dispute: Plaintiff alleges that Defendant’s graphics processing units (GPUs) and related products implementing the Fermi, Kepler, Maxwell, Pascal, and Volta architectures infringe four patents related to foundational graphics processing techniques.
  • Technical Context: The lawsuit concerns core technologies in 3D graphics rendering, a critical component for markets ranging from personal computing and professional workstations to high-performance gaming.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of the patents-in-suit. Plaintiff allegedly provided notice of the ’355, ’800, and ’156 patents in August 2013, and notice of the ’659 patent in November 2016, which forms the basis for the willfulness allegations. The complaint also notes that Intel Corporation took a license to Plaintiff's patent portfolio in November 2012.

Case Timeline

Date Event
1998-07-17 '355 Patent Priority Date
2001-01-30 '355 Patent Issue Date
2001-02-27 '800 Patent Priority Date
2003-12-31 '156 Patent Priority Date
2003-12-31 '659 Patent Priority Date
2005-05-31 '800 Patent Issue Date
2012-03-27 '156 Patent Issue Date
2012-11 Intel acquires license to ZiiLabs' patent portfolio
2013-08-07 Nvidia receives notice of '355, '800, and '156 Patents
2014-02-04 '659 Patent Issue Date
2016-11 Nvidia receives notice of '659 Patent
2017-12-27 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,181,355 - “Graphics Processing with Transcendental Function Generator,” issued January 30, 2001

The Invention Explained

  • Problem Addressed: The patent describes that processing 3D graphics often requires performing specialized mathematical calculations known as transcendental functions (e.g., inverse square root, powers of 2) on vertex data. Conventionally, this required dedicated hardware and a separate lookup table for each specific function, which could be inefficient. (’355 Patent, col. 1:25-38).
  • The Patented Solution: The invention proposes a more flexible and efficient graphics processor architecture. It uses a single, shared "interpolation engine" that receives an instruction telling it which of several available lookup tables to use for a given calculation. This allows a single hardware unit to be dynamically configured to perform different transcendental functions as needed, rather than requiring multiple, dedicated hardware blocks. (’355 Patent, Abstract; col. 2:1-8; Fig. 3).
  • Technical Importance: This approach provided a method for increasing the functional density and flexibility of geometry accelerators in GPUs, allowing for more efficient hardware utilization when performing common vertex processing operations. (’355 Patent, col. 1:32-38).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 7, among others (Compl. ¶4, ¶26).
  • Independent Claim 1 requires:
    • An input for receiving an instruction for processing a given vertex.
    • Memory for storing a first lookup table and a second lookup table, each corresponding to a different function.
    • An interpolation engine that, in response to the instruction, selects one of the lookup tables, determines an output from it, and produces a final value based on that output and vertex data.
  • The complaint reserves the right to assert additional claims, including dependent claims (Compl. ¶4).

U.S. Patent No. 6,900,800 - “Tile Relative Origin for Plane Equations,” issued May 31, 2005

The Invention Explained

  • Problem Addressed: A fundamental task in 3D rendering is determining if a pixel lies inside a given polygon (e.g., a triangle). This is often done using "plane equations." The patent notes that if the polygon is located far from the screen's coordinate origin (0,0), the constant term in these equations can become very large, requiring wider data paths and more complex, power-hungry arithmetic logic in the GPU. (’800 Patent, col. 1:17-21; col. 2:42-51).
  • The Patented Solution: The invention proposes performing these calculations relative to a local origin that is close to the polygon being rendered, rather than the fixed global origin of the screen. By using a "tile relative origin," the magnitude of the values in the plane equation is significantly reduced. This simplifies the necessary hardware, reduces the required dynamic range for calculations, and improves efficiency. (’800 Patent, Abstract; col. 2:52-59).
  • Technical Importance: This technique offered a way to manage computational complexity and hardware costs in the rasterization stage of the graphics pipeline, particularly as screen resolutions and the complexity of 3D scenes increased. (’800 Patent, col. 2:57-59).

Key Claims at a Glance

  • The complaint asserts independent claim 1, among others (Compl. ¶4, ¶40).
  • Independent Claim 1 is a method claim requiring the steps of:
    • Evaluating plane equations at a "base location which is not external to the patch" of pixels being processed.
    • Computing plane equation "valuation offsets" for various spatial offsets from that base location.
    • Using these offsets to determine if pixels in the patch are part of the primitive.
  • The complaint reserves the right to assert additional claims (Compl. ¶4).

U.S. Patent No. 8,144,156 - “Sequencer with Async SIMD Array,” issued March 27, 2012

  • Technology Synopsis: The patent addresses the problem of processing elements (PEs) in a Single Instruction, Multiple Data (SIMD) array sitting idle when the central instruction sequencer stalls (e.g., waiting for a memory access). The invention decouples the sequencer from the PE array using a FIFO buffer, allowing the PEs to continue executing instructions from the buffer while the sequencer handles other tasks, which may improve overall hardware utilization. (’156 Patent, Abstract; col. 3:13-25).
  • Asserted Claims: Claims 1-20 are asserted, with claim 1 being representative (Compl. ¶4, ¶54).
  • Accused Features: The complaint alleges that the general architecture of the Accused Products, which employ SIMD arrays and sequencers, infringes this patent (Compl. ¶53-54).

U.S. Patent No. 8,643,659 - “Shader with Global and Instruction Caches,” issued February 4, 2014

  • Technology Synopsis: The patent addresses the physical memory limitations on the size and complexity of shader programs running on a GPU. The invention proposes using instruction and global data caches to "virtualize" the shader memory. When a shader needs data or an instruction not present in the on-chip cache (a "cache miss"), it is fetched from larger, external memory, allowing for shaders that are much larger than what could be stored in on-chip registers or WCS alone. (’659 Patent, Abstract; col. 1:38-49).
  • Asserted Claims: Claims 1-20 are asserted, with claim 1 being representative (Compl. ¶4, ¶68).
  • Accused Features: The complaint alleges that the memory and caching architectures within the Accused Products, used for handling shader programs, infringe this patent (Compl. ¶67-68).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies the accused instrumentalities as a broad class of Defendant's products, including "graphics cards, GPUs, and GPU designs implementing Defendant's Fermi, Kepler, Maxwell, Pascal, and Volta architectures" (Compl. ¶5).
  • Functionality and Market Context: The Accused Products are high-performance graphics processors that form the core of Defendant's graphics card offerings for the consumer, gaming, and professional markets (Compl. ¶1, ¶5). The complaint alleges these products are pre-programmed to perform the functions described in the asserted patents, including processing transcendental functions, performing tile-based rendering calculations, and utilizing asynchronous processing and caching for shader programs (Compl. ¶30, ¶44, ¶58, ¶72). Plaintiff's predecessor, 3DLabs, is positioned as an "early pioneer in the creation of a 3D graphics chip" (Compl. ¶10).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits for each asserted patent; however, these exhibits were not filed with the complaint document (Compl. ¶26, ¶40, ¶54, ¶68). The analysis below is based on the narrative allegations. No probative visual evidence provided in complaint.

  • ’355 Patent Infringement Allegations: The complaint alleges that the Accused Products are "pre-programmed to function in the manner claimed in the '355 Patent," infringing at least claim 7 (Compl. ¶26, ¶29). The infringement theory suggests that Defendant's GPUs contain hardware, corresponding to the claimed "interpolation engine," that selects from different lookup tables to perform various transcendental functions required for 3D graphics rendering.
  • ’800 Patent Infringement Allegations: The complaint alleges that the Accused Products infringe at least claim 1 because they are "pre-programmed to function in the manner claimed in the '800 Patent" (Compl. ¶40, ¶44). The narrative theory is that Defendant’s GPUs, when rasterizing polygons, evaluate plane equations relative to a local origin near the tile or patch of pixels being processed, thereby meeting the limitations of calculating from a "base location which is not external to the patch."
  • Identified Points of Contention:
    • Scope and Technical Questions (’355 Patent): A central question will be whether the architecture of the Accused Products maps onto the elements of the asserted claims. For example, does the hardware for mathematical operations in a modern Nvidia GPU constitute an "interpolation engine" that "selects one of the lookup tables" based on a discrete "instruction" in the manner required by claim 1? The analysis may turn on how these functional blocks are defined and implemented in the accused architectures.
    • Scope and Technical Questions (’800 Patent): The infringement analysis will likely focus on the specific implementation of rasterization in the accused GPUs. A key question is whether Defendant's process for determining pixel membership within a primitive relies on calculating plane equations from a "base location" that is "not external to the patch," as claimed. Evidence from the design and operation of the accused rasterizers will be required to resolve this.

V. Key Claim Terms for Construction

  • The Term: "interpolation engine" (’355 Patent, claim 1)

    • Context and Importance: This term defines the core functional unit of the invention. Its construction is critical because the infringement analysis depends on whether the hardware in Defendant's GPUs that performs mathematical calculations qualifies as the claimed "interpolation engine."
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim language itself is functional, describing an engine that "produces an output value based upon the table output and data relating to the given vertex" (col. 8:17-21). This could support a reading that covers any hardware performing this function.
      • Evidence for a Narrower Interpretation: The specification describes a specific embodiment where a "multiplexer" (MUX 306) is used to "selectably couple" the engine to one of several tables based on an instruction (col. 2:5-8, Fig. 3). This may support an argument that the term requires a distinct selection mechanism from a plurality of discrete tables.

  • The Term: "base location which is not external to the patch" (’800 Patent, claim 1)

    • Context and Importance: This limitation is central to the patent's claimed advance over prior art methods that used a fixed, global origin. The definition of "patch" and the proximity required by "not external" will be determinative for infringement.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The term itself suggests a flexible standard, merely requiring the reference point not be distant from the area of interest. The patent states the goal is to "reduce the dynamic range of C" by selecting a "new origin closer to the triangle" (col. 3:28-32), supporting a functional interpretation.
      • Evidence for a Narrower Interpretation: The specification provides specific examples, stating the "base point" is "within or adjacent to the patch of pixels being tested" (col. 2:55-57) and that the origin can be the "(0,0) fragment position of the upper left tile which touches the primitive" (col. 4:13-16). This could be used to argue for a narrower definition tied to specific tile-based architectures and locations.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all four patents. Inducement is based on allegations that Defendant provides user guides, technical support, and marketing materials that instruct and encourage end-users to operate the Accused Products in an infringing manner (e.g., Compl. ¶29, ¶43, ¶57, ¶71). Contributory infringement is based on allegations that the products are "specifically made and/or specifically adapted" for infringement and are not "staple commodities of commerce" suitable for substantial non-infringing use (e.g., Compl. ¶32, ¶46, ¶60, ¶74).
  • Willful Infringement: Willfulness is alleged for all four patents. The allegations are based on Defendant's alleged pre-suit knowledge via notice letters sent on August 7, 2013 (for the ’355, ’800, and ’156 patents) and in November 2016 (for the ’659 patent), followed by continued alleged infringement (e.g., Compl. ¶33, ¶47, ¶61, ¶75).

VII. Analyst’s Conclusion: Key Questions for the Case

  • Evidentiary Proof vs. Architectural Complexity: A primary issue will be whether Plaintiff can produce sufficient evidence from Defendant's highly complex and proprietary GPU designs to demonstrate that they practice the specific methods claimed. The case may hinge on whether the foundational techniques described in these patents are identifiably present within the highly evolved and abstracted architectures of modern GPUs.
  • Claim Scope in a Modern Context: The dispute will test the reach of patent claims drafted for the GPU technologies of the late 1990s and early 2000s against today's vastly more powerful and complex processors. A central question for the court will be one of definitional scope: can terms like "interpolation engine" and "base location" be construed to cover the analogous, but potentially far more sophisticated, functional blocks and processes within Nvidia’s Fermi-to-Volta architectures?
  • The Impact of Pre-Suit Notice: The allegations of willfulness are grounded in specific dates of notice. A key question for damages will be whether Defendant's continued sales after receiving these notices constituted objective recklessness, potentially exposing Defendant to enhanced damages if infringement is found.