DCT

1:18-cv-00307

ProMOS Tech Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:18-cv-00307, D. Del., 11/21/2018
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Samsung Austin Semiconductor, LLC is a Delaware limited liability corporation and thus resides in the district. The complaint further alleges that Samsung conducts regular business and has committed acts of infringement in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s DRAM products, and the processes used to manufacture them, infringe five U.S. patents related to semiconductor circuit design and fabrication technology.
  • Technical Context: The dispute centers on the design and manufacture of Dynamic Random-Access Memory (DRAM), a fundamental component for data storage in a vast range of modern electronic devices.
  • Key Procedural History: The complaint alleges that Plaintiff placed Defendant on notice of infringement for the '492, '559, and '201 patents via a letter on August 21, 2017, and for the '974 and '386 patents via a letter on October 31, 2017. These pre-suit notice allegations form the basis for the willfulness claims.

Case Timeline

Date Event
1997-11-05 '974 Patent Priority Date
1998-10-23 '492 Patent Priority Date
1999-03-04 '386 Patent Priority Date
1999-08-10 '974 Patent Issued
2000-02-28 '201 Patent Priority Date
2000-04-03 '559 Patent Priority Date
2000-08-08 '386 Patent Issued
2000-12-19 '492 Patent Issued
2002-10-22 '559 Patent Issued
2003-07-22 '201 Patent Issued
2017-08-21 Notice of infringement for '492, '559, '201 patents alleged to be sent
2017-10-31 Notice of infringement for '974, '386 patents alleged to be sent
2018-11-21 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,163,492 - "Programmable Latches that Include Non-volatile Programmable Elements," Issued December 19, 2000

The Invention Explained

  • Problem Addressed: The patent describes a problem in prior art programmable latches where, after a programming fuse is blown, the latch's output terminal can "float" to an unstable or incorrect voltage level during power-up, potentially causing circuit malfunction ('492 Patent, col. 1:36-48). Conventional solutions, such as using a bypass capacitor, were seen as undesirable because they depend on the rate at which power is supplied ('492 Patent, col. 1:49-54, col. 2:62-64).
  • The Patented Solution: The invention proposes a programmable latch that includes a diode connected between the latch's output terminal and a power or reference voltage terminal ('492 Patent, Abstract). This diode is designed to keep the voltage on the output terminal within a predetermined, stable range before power is supplied to the latch, thereby preventing an incorrect state upon power-up without relying on a delay capacitor ('492 Patent, col. 2:2-11).
  • Technical Importance: This design improves the power-on reliability of integrated circuits that use programmable elements for post-fabrication configuration, such as repairing defective memory cells with spare cells ('492 Patent, col. 1:19-24).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 14 (Compl. ¶26).
  • Independent Claim 1 recites the following essential elements:
    • A first terminal for receiving a first voltage and a second terminal for receiving a second voltage.
    • An output terminal (T1) indicating the latch's state.
    • A programmable electrical path (e.g., a fuse) between the first terminal and terminal T1.
    • A variable-impedance electrical path (e.g., a transistor) between terminal T1 and the second terminal, where the impedance is controlled by a signal on terminal T1.
    • A diode for keeping the voltage on terminal T1 within a predetermined range before power is supplied to the latch.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,469,559 - "System and Method for Eliminating Pulse Width Variations in Digital Delay Lines," Issued October 22, 2002

The Invention Explained

  • Problem Addressed: In digital systems, particularly those with Delay Locked Loops (DLLs), long chains of inverters are used to create precise time delays. However, process variations in the transistors of these inverters can cause the propagation delays for rising and falling signal edges to differ, leading to a distortion of the signal's pulse width as it travels through the chain ('559 Patent, col. 1:35-51).
  • The Patented Solution: The patent discloses partitioning a delay line into two "substantially identical" blocks of delay elements. A first inverter is inserted between the two blocks, and a second, substantially identical inverter is placed at the output of the second block ('559 Patent, Abstract; col. 2:10-24). Because the first inverter flips the signal polarity, a rising edge entering the first block becomes a falling edge entering the second, and vice-versa. This architecture ensures that both rising and falling edges experience the same cumulative delay characteristics, thereby preserving the original pulse width ('559 Patent, col. 2:25-34).
  • Technical Importance: This method provides robust signal integrity for high-speed timing circuits, which is critical for applications like Double Data Rate (DDR) memory that rely on accurate clocking to transfer data on both edges of a clock cycle ('559 Patent, col. 1:35-41).

Key Claims at a Glance

  • The complaint asserts independent claims 5 and 14 (Compl. ¶43).
  • Independent Claim 5 recites the following essential elements:
    • First and second blocks of delay elements, where individual delay elements within the blocks are at least partially unequal, but the blocks themselves have "substantially identical block level integrated circuit layouts."
    • A first non-voltage controlled inverter coupled to the output of the first block.
    • A second non-voltage controlled inverter coupled to the output of the second block.
    • A condition wherein the propagation delay of the first and second inverters is equal.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,597,201 - "Dynamic Predecoder Circuitry for Memory Circuits," Issued July 22, 2003

  • Technology Synopsis: The patent addresses the speed, power, and size limitations of conventional static predecoder circuits in memory devices ('201 Patent, col. 1:25-52). The invention discloses a predecoder built around a dynamic NAND gate, which is alleged to be faster, consume less power, occupy less chip area, and enable the use of a shared address bus for multiple memory banks ('201 Patent, col. 2:12-25).
  • Asserted Claims: At least claim 1 (Compl. ¶56).
  • Accused Features: The predecoder circuits in Samsung DRAM, which are alleged to use a dynamic NAND gate to predecode address selection signals for a memory circuit (Compl. ¶57-58). The complaint includes an annotated schematic of the accused predecoder, identifying the "dynamic NAND gate" and its constituent "first circuit element" and "second circuit element" (Compl. ¶62).

U.S. Patent No. 5,934,974 - "In-Situ Monitoring of Polishing Pad Wear," Issued August 10, 1999

  • Technology Synopsis: The patent addresses the challenge of determining when to replace polishing pads used in Chemical Mechanical Polishing (CMP), a key semiconductor manufacturing process. Replacing pads based on a fixed number of wafers is inefficient ('974 Patent, col. 1:30-38). The invention describes a method and system for measuring pad wear in-situ (during the polishing process) using a sensor, enabling real-time monitoring and more efficient maintenance scheduling and process control ('974 Patent, Abstract).
  • Asserted Claims: At least claim 28 (Compl. ¶72).
  • Accused Features: Samsung’s semiconductor manufacturing processes are alleged to use a CMP tool that measures polishing pad thickness during polishing to generate a pad profile, which is then analyzed to adjust operating parameters and reduce pad wear non-uniformities (Compl. ¶73-76).

U.S. Patent No. 6,099,386 - "Control Device for Maintaining a Chemical Mechanical Polishing Machine in Wet Mode," Issued August 8, 2000

  • Technology Synopsis: The patent describes the problem of residual chemical slurry drying on a CMP machine's polishing pad and other components when the machine is idle, which can lead to solidified debris that causes defects on subsequently processed wafers ('386 Patent, col. 1:48-58). The invention is a control device that senses when the slurry sprinkler has been inactive for a predetermined period and automatically activates it to sprinkle liquid, thereby maintaining the machine in a "wet mode" to prevent drying ('386 Patent, Abstract).
  • Asserted Claims: At least claim 1 (Compl. ¶80).
  • Accused Features: Samsung is accused of using a CMP tool that includes a control device to maintain the polishing pad in a wet mode. This is allegedly achieved by using a flow sensor to detect when the slurry sprinkler is idle and a control unit that, after a predetermined time, turns the sprinkler on to apply liquid and prevent drying (Compl. ¶81, 83-84).

III. The Accused Instrumentality

  • Product Identification: The complaint primarily accuses Samsung’s DRAM products, with the "K4B2G0846D-HCH9 2 Gb DDR3 SDRAM" identified as a specific exemplary product (Compl. ¶26). The allegations are also extended to a wide range of other Samsung memory products, including DDR4, LPDDR3, LPDDR4, LPDDR4X, LPDDR5, GDDR3, GDDR4, GDDR5, and GDDR6 DRAM (Compl. ¶35). For the '974 and '386 patents, the accused instrumentalities are the processes and tools, respectively, used in Samsung's semiconductor manufacturing facilities (Compl. ¶69, 79).
  • Functionality and Market Context: The accused DRAM products are semiconductor memory chips that provide high-speed data storage for consumer electronics, mobile phones, and computer components (Compl. ¶2). The complaint alleges these products contain specific circuitry that performs the functions of programmable latching, signal delay, and address predecoding (Compl. ¶26, 43, 56). The complaint references Samsung’s own marketing materials to assert its position as a market leader in "main memory" manufacturing (Compl. ¶3). The complaint provides an annotated schematic of the accused "Fuse Cell 1" circuit, identifying elements such as "a 1st terminal", "a non-volatile programmable element", and "an inverter" (Compl. ¶34).

IV. Analysis of Infringement Allegations

'492 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a programmable latch comprising: a first terminal for receiving a first voltage; Samsung DRAM contains programmable latches with a first terminal that receives a high voltage. ¶27 col. 8:6-12
a second terminal for receiving a second voltage; The programmable latches also contain a second terminal that receives a lower voltage than the first terminal. ¶28 col. 8:6-12
a terminal T1 for providing a signal indicating a state of the programmable latch; The programmable latches further contain a terminal T1 which provides an output signal having a state which indicates the state of the programmable latch. ¶29 col. 8:13-15
a programmable electrical path including a non-volatile programmable element...when the programmable element is conductive, the programmable path connects the terminal T1 to the first terminal... The programmable latches also have a fuse that when conductive connects the terminal T1 to the first terminal, and when not conductive does not connect the terminal T1 to the first terminal. ¶30 col. 8:16-24
a variable-impedance electrical path between the terminal T1 and the second terminal, wherein the impedance of the electrical path is controlled by a signal on the terminal T1; The programmable latches also contain an NMOS transistor between terminal T1 and the second terminal, and the impedance of the path is controlled by a signal on the terminal T1, which is supplied by an inverter connected to the terminal T1. ¶31, ¶33 col. 8:25-29
a diode for keeping a voltage on the terminal T1 within a predetermined range of values before power is supplied to the latch... At least one of the programmable latches contains a PMOS transistor that operates as a diode for keeping a voltage on the terminal T1 within a predetermined range of values before power is supplied to the latch. ¶32 col. 8:30-35
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the phrase "a diode" in the claim can be construed to read on the accused "PMOS transistor that operates as a diode" (Compl. ¶32). The dispute could focus on whether the claim requires a dedicated two-terminal diode structure or if it covers any component configured to perform the specified function.
    • Technical Questions: The claim requires the diode to function before power is supplied. A key evidentiary question will be what proof exists that the accused transistor performs this specific pre-power-up voltage clamping function, as opposed to other functions it may perform once the circuit is powered.

'559 Patent Infringement Allegations

A circuit schematic is provided to illustrate the alleged infringing delay line, annotating the "1st block of delay elements", the "1st non-voltage controlled inverter", and noting that the "Propagation delay of the first and second inverters is equal" (Compl. ¶49).

Claim Element (from Independent Claim 5) Alleged Infringing Functionality Complaint Citation Patent Citation
first and second blocks of delay elements...wherein the propagation delay of individual delay elements in each of said first and second blocks is at least partially unequal... Samsung DRAM's delay lines have first and second blocks of inverters...wherein the transistors in the inverters are sized differently resulting in different propagation delays between elements within each block. ¶45 col. 6:10-13
...and said first and second blocks have substantially identical block level integrated circuit layouts; The first and second blocks have identical sets of transistors, and the blocks also have substantially identical propagation delays. ¶45 col. 6:13-15
a first non-voltage controlled inverter coupled to an output of said first block of delay elements... The delay lines also contain a first non-voltage controlled inverter coupled to the output of the first blocks of inverters. ¶46 col. 6:16-19
a second non-voltage controlled inverter coupled to an output of said second block of delay elements... The delay lines further contain a second non-voltage controlled inverter coupled to the output of the second blocks of inverters. ¶47 col. 6:20-23
wherein the propagation delay of said first and second inverters is equal. The first and second non-voltage controlled inverters...have the same layout and are identically sized, which contributes to equal propagation delay through the inverters. ¶48 col. 6:24-26
  • Identified Points of Contention:
    • Scope Questions: The claim requires "substantially identical block level integrated circuit layouts." The interpretation of "substantially identical" will be critical. This raises the question of what degree of physical and electrical similarity is required to meet this limitation.
    • Technical Questions: The infringement theory rests on a dual condition: individual elements within the blocks are "partially unequal," while the blocks themselves are "substantially identical" (Compl. ¶45). A factual dispute may arise over whether the accused circuits simultaneously satisfy both of these potentially conflicting characteristics.

V. Key Claim Terms for Construction

'492 Patent: "diode" (Claim 1)

  • Context and Importance: This term is critical because the complaint alleges that a "PMOS transistor that operates as a diode" meets this limitation (Compl. ¶32). The core of the infringement question for this element will depend on whether the claim term "diode" is limited to a traditional two-terminal semiconductor device or can encompass a multi-terminal transistor configured to function as one.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent specification describes the function of the diode as "keeping a voltage on a latch output terminal within a predetermined range" ('492 Patent, col. 2:2-5). A party could argue that any structure performing this explicitly stated function meets the limitation, regardless of its specific form.
    • Evidence for a Narrower Interpretation: The detailed embodiment shown in Figure 2B illustrates the diode as a distinct P+ region within an N-well, forming a classic PN junction ('492 Patent, Fig. 2B). A party could argue that this specific implementation limits the scope of "diode" to such a structure, excluding a configured transistor.

'559 Patent: "substantially identical block level integrated circuit layouts" (Claim 5)

  • Context and Importance: This phrase captures the essence of the patented solution: creating two matched halves of a delay line. The complaint alleges infringement based on blocks having "identical sets of transistors" and "substantially identical propagation delays" (Compl. ¶45). Practitioners may focus on this term because the factual determination of whether two complex circuit layouts are "substantially identical" is a common point of dispute.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The word "substantially" inherently allows for some deviation from perfect identity. The purpose of the invention is to preserve pulse width by matching delay characteristics ('559 Patent, col. 2:32-34). An argument could be made that any layout differences that do not materially affect this functional outcome are encompassed by "substantially identical."
    • Evidence for a Narrower Interpretation: The summary of the invention states that "the same identical layout can be used for the first and second blocks" ('559 Patent, col. 2:22-24). This language may support an argument that the patentee envisioned near-perfect geometric and topological identity, not just functional equivalence, for the layouts.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents, claiming Samsung advertises, promotes, and provides instructions or technical support for its DRAM products, knowing and intending that its customers will use them in an infringing manner (Compl. ¶36, 51, 67, 70-71, 79). For the '201 patent, the complaint also alleges contributory infringement, stating the accused DRAMs are especially made for infringement and have no substantial non-infringing use (Compl. ¶64, 66).
  • Willful Infringement: The complaint alleges that Samsung has had knowledge of the patents-in-suit since receiving notice letters from ProMOS on August 21, 2017, and October 31, 2017 (Compl. ¶37, 52, 65, 77, 85). The allegation of continued infringement after receiving notice serves as the basis for the claim of willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "diode" in the '492 patent, shown in an embodiment as a simple PN junction, be construed to cover a "PMOS transistor that operates as a diode"? Similarly, what degree of physical and electrical similarity is required for two circuit blocks to possess "substantially identical block level integrated circuit layouts" as claimed in the '559 patent?
  • A key evidentiary question will be one of operational proof: for the manufacturing patents ('974 and '386), what evidence demonstrates that Samsung’s commercial-scale CMP processes practice the specific in-situ monitoring, analysis, and wet-mode maintenance steps as claimed?
  • A third question concerns the breadth of the infringement claims: the complaint identifies a single DDR3 part as exemplary but extrapolates infringement to numerous subsequent DRAM generations. A central dispute will likely be whether the specific accused circuit designs and manufacturing processes are in fact present across this wide and diverse range of accused products.