DIFF Scale Operation Research LLC v. Cypress Semiconductor Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: DIFF Scale Operation Research, LLC (Delaware)
  • Defendant: Cypress Semiconductor Corporation (Delaware)
  • Plaintiff’s Counsel: Bayard, P.A.; Berger & Hipskind LLP
• Case Identification: 1:18-cv-00372, D. Del., 03/08/2018
• Venue Allegations: Venue is alleged to be proper based on Defendant being a Delaware corporation that has transacted business and committed acts of infringement in the District of Delaware.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including timing devices and physical layer transceivers, infringe patents related to phase-locked loops (PLLs) and adaptive clock recovery in packet networks.
• Technical Context: The technology concerns methods for maintaining stable and accurate clock signals in telecommunications systems, which is critical for synchronizing data transmission and preventing data loss.
• Key Procedural History: The complaint notes that the asserted patent portfolio originated with ADC Telecommunications, Inc. A portion of ADC's portfolio was sold to HTC in 2011 and asserted against Apple, which the complaint frames as evidence of the portfolio's value. The patents-in-suit were later assigned from CommScope, Inc. (which acquired ADC) to the Plaintiff to facilitate licensing.

Case Timeline

Date	Event
1999-11-19	Priority Date for ’328 Patent
2001-03-02	Priority Date for ’413 and ’827 Patents
2003-12-16	Issue Date for U.S. Patent No. 6,664,827
2004-04-13	Issue Date for U.S. Patent No. 6,721,328
2011-02-01	Issue Date for U.S. Patent No. 7,881,413
2017-12-01	Date of Accused Product Datasheet (CY23FS04)
2018-03-08	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,881,413 - Digital PLL with Conditional Holdover, Issued Feb. 1, 2011

The Invention Explained

• Problem Addressed: In communication systems, timing signals must be maintained even if the reference clock signal is lost or degraded, to avoid data loss. However, simply using a prior control signal ("holdover") can be inaccurate due to long-term drift or noise preceding the signal loss (’413 Patent, col. 2:3-17). Furthermore, different timing sources have different quality levels (strata), and a system needs a way to intelligently select the best available source (’413 Patent, col. 2:13-54).
• The Patented Solution: The invention provides a phase-locked loop (PLL) with a "conditional holdover" capability. It uses a processor to monitor a status message (like a SONET/SDH SSM) that indicates the quality level of an incoming reference clock signal. The PLL can be selectively placed into a holdover state (generating its own timing) based on this quality message, not just on signal loss, ensuring the system uses a timing source of a certain minimum quality (’413 Patent, col. 3:10-29; Fig. 4).
• Technical Importance: This approach allows a network element to make more sophisticated, quality-based decisions about its timing source, potentially avoiding timing errors that could occur by locking to a degraded but still present reference signal (’413 Patent, col. 2:55-62).

Key Claims at a Glance

• Independent claim 21 is asserted (Compl. ¶65).
• Claim 21 (System): A network element comprising:
  • a shelf backplane;
  • a plurality of shelf elements coupled to the backplane, including at least one shelf controller;
  • the shelf controller comprising a processor and a timing circuit;
  • the timing circuit including a receiver, a framer, and a second phase-locked loop;
  • the second PLL comprising a digital phase comparator, a digital loop filter, a numerically-controlled oscillator, and a processor coupled to the digital phase comparator;
  • a machine-readable medium with instructions for the processor to monitor the digital phase comparator, detect a step change in phase relationship, and recenter the comparator if a step change is detected.
• The complaint reserves the right to assert other claims (Compl. ¶68).

U.S. Patent No. 6,664,827 - Direct Digital Synthesizer Phase Locked Loop, Issued Dec. 16, 2003

The Invention Explained

• Problem Addressed: Conventional PLLs can encounter problems with "a step change in the incoming reference clock signal," which can occur when switching between timing sources. A typical PLL will attempt to track this abrupt change, causing a disruption in its output frequency until it re-locks (’827 Patent, col. 2:18-23). Another issue is the long-term frequency drift of crystal oscillators used in PLLs (’827 Patent, col. 2:1-4).
• The Patented Solution: The patent describes a PLL that uses a processor to monitor the phase comparator for a "step change." Upon detecting such a change, the processor can "recenter" the phase comparator, suppressing the tracking of the step change and mitigating the output disruption. This is achieved by adjusting the relationship between frequency divider counters in the loop (’827 Patent, col. 8:39-65). The invention also describes using a low-pass filter to average the control signal over time, allowing the processor to detect and compensate for long-term oscillator drift (’827 Patent, col. 9:26-47).
• Technical Importance: This solution provides a more robust PLL that can handle abrupt changes in reference signals without significant output disruption and can also correct for long-term drift, improving overall timing stability in communication systems (’827 Patent, col. 2:29-44).

Key Claims at a Glance

• Independent claim 28 is asserted (Compl. ¶94).
• Claim 28 (Method on Machine-Readable Medium): Instructions to cause a processor to perform a method comprising:
  • sampling values of an error signal, where the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal;
  • monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal; and
  • recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected.
• The complaint reserves the right to assert other claims (Compl. ¶97).

U.S. Patent No. 6,721,328 - Adaptive Clock Recovery for Circuit Emulation Service, Issued Apr. 13, 2004

Technology Synopsis

The patent addresses clock recovery in packet networks like ATM, where data arrives in "bursty" fashion, causing variations in a destination node's buffer fill level. The invention proposes using the "peak" or "relative maximum" buffer fill level over a period of time as a stable indicator to control the frequency of a local clock, thereby locking it to the source clock while filtering out jitter caused by network delay variations (’328 Patent, col. 2:1-17, Abstract).

Asserted Claims

Independent claim 1 is asserted (Compl. ¶119).

Accused Features

The complaint alleges that Cypress's Backplane Physical Layer (PHY) devices, which include "Elasticity Buffers," infringe the '328 Patent. The complaint points to block diagrams showing these buffers and alleges they are used to control the rate at which data is transmitted (’328 Patent, ¶¶103, 110-118).

III. The Accused Instrumentality

Product Identification

• ’413 Products: Timing devices including CY2292, CY23FS04, CY26049-36, CY7B9945V, CYP15G0401DXB, and CYV15G0401DXB (Compl. ¶48).
• ’827 Products: Timing devices including CY7B9973V, CY7B9945V, and others in the RoboClock family (Compl. ¶74).
• ’328 Products: Backplane Physical Layer (PHY) devices including CYV15G0204RB, CYP15G0401DXB, and others (Compl. ¶103).

Functionality and Market Context

• The accused products are semiconductor components used for timing and data transmission in electronic systems (Compl. ¶¶1, 73, 102). The complaint alleges the ’413 Products provide a "redundant clock source in the event of a reference clock failure" by using a Digitally Controlled Crystal Oscillator (DCXO) that maintains the last frequency and phase of a reference clock (Compl. ¶¶51, p. 20).
• The complaint alleges the ’827 Products perform "lock detection" by "comparing the phase difference between the reference and feedback inputs" and can enter an "out-of-lock state" after consecutive phase errors, requiring consecutive errorless cycles to re-establish a lock (Compl. ¶¶77, 90).
• The complaint alleges the ’328 Products are transceivers that use "Elasticity Buffers" to receive and store data packets, with clocking functions to control the data transmission rate out of the buffer (Compl. ¶¶110, 117-118). The complaint includes a block diagram from a datasheet with the added annotation, "Buffers Where Data Is Received And Stored In The Cypress Products" (Compl. p. 31).

IV. Analysis of Infringement Allegations

’413 Patent Infringement Allegations

Claim Element (from Independent Claim 21)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a second phase locked loop coupled to receive the second reference clock signal and to generate a timing signal therefrom...	Cypress products are alleged to use a phase-locked loop (PLL) to generate a timing signal. A logic block diagram from a Cypress datasheet showing a "PLL" block is provided as evidence.	¶¶57, 60; p. 21	col. 16:19-22
the second phase locked loop comprising...a processor coupled to the digital phase comparator; and a machine-readable medium having instructions stored thereon...	The accused products are alleged to contain a system for performing elements in a prescribed order. An annotated graphic asserts, "The Cypress Product Place The PLL In Holdover Using An Ordered Step Process."	¶¶61, 64; p. 22	col. 18:6-14
to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and the feedback signal...	The accused products are alleged to include functionality for monitoring a status message from a reference clock source indicative of its quality level.	¶62	col. 18:15-18
and to recenter the digital phase comparator if a step change is detected	The accused products are alleged to contain a system for placing the PLL in a holdover condition if the quality level indicated by a status message is below a target level. A product datasheet is cited, stating the device serves as a "redundant clock source in the event of a reference clock failure."	¶¶51, 63; p. 20	col. 18:18-21

Identified Points of Contention

• Scope Questions: The asserted claim 21 recites detecting a "step change" and "recentering" the comparator, language that more closely aligns with the technology of the '827 Patent. The complaint's narrative for the '413 patent focuses on "conditional holdover" based on a "quality level" (Compl. ¶¶62-63). A central question may be whether the accused product's operation, described as entering holdover on "reference clock failure," meets the specific "step change detection" and "recenter" limitations of claim 21.
• Technical Questions: What evidence does the complaint provide that the accused product's "Failsafe Block" (Compl. p. 21) performs the functions of a "processor" with "machine-readable instructions" that "monitors" and "recenters" a phase comparator, as recited in the claim? The complaint's allegations are largely functional and conclusory.

’827 Patent Infringement Allegations

Claim Element (from Independent Claim 28)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal;	The accused products are alleged to contain a Phase Frequency Detector that accepts signals from reference and feedback inputs and generates correction information, which constitutes an error signal.	¶¶84, 89; p. 26	col. 20:2-6
monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal; and	The accused product documentation allegedly states that after "four or more consecutive feedback clock cycles with phase-errors, the LOCK output is forced LOW to indicate out-of-lock state."	¶90; p. 27	col. 20:7-11
recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected.	The accused product allegedly attempts to "recenter" after an "out-of-lock state" is declared, requiring "32 consecutive phase-errorless feedback clock cycles" to return to a "lock condition."	¶¶90, 93; p. 27	col. 20:12-15

Identified Points of Contention

• Scope Questions: Does the accused product's process of entering an "out-of-lock state" and requiring a number of "phase-errorless" cycles to re-lock (Compl. p. 27) constitute "recentering a phase comparator" as the term is used in the patent? The patent describes recentering by adjusting divider counters to mitigate a step change without moving the timing signal phase, which may be a more specific operation than what the datasheet describes (’827 Patent, col. 8:39-65).
• Technical Questions: The complaint alleges infringement based on datasheets describing the functional behavior of the lock detector. A key question will be whether the underlying circuitry and software of the accused products actually perform the method steps as claimed, particularly the specific act of "recentering" a comparator rather than simply having the PLL reacquire lock through its normal feedback mechanism.

V. Key Claim Terms for Construction

For the ’413 Patent (re: Claim 21)

• The Term: "recenter the digital phase comparator"
• Context and Importance: This term is central to the infringement analysis for claim 21. The complaint's infringement theory for the '413 patent focuses on "conditional holdover" based on quality messages, while the asserted claim recites "recentering." The viability of the infringement claim may depend on whether the accused functionality can be construed as "recentering."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not appear to provide an explicit definition. A party might argue that any action that restores the comparator to a normal operating point after a disruption, such as the accused product's re-synchronization after a reference clock is restored (Compl. p. 20), constitutes "recentering."
  • Evidence for a Narrower Interpretation: The specification of the related '827 patent, filed on the same day by the same inventor and incorporated by reference into the '413 prosecution history, describes "recenter[ing] the phase comparator" in specific detail as adjusting divide-by-N counters to mitigate a step change without moving the phase of the timing signal (’827 Patent, col. 8:39-65). A party may argue this specific mechanism defines the term's scope.

For the ’827 Patent (re: Claim 28)

• The Term: "step change"
• Context and Importance: The entire method of claim 28 is triggered by the detection of a "step change." The infringement allegation relies on a datasheet describing the product going into an "out-of-lock state" after "four or more consecutive feedback clock cycles with phase-errors" (Compl. p. 27). Whether this condition meets the definition of a "step change" will be critical.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes a step change as a problem encountered in PLLs, including "a step change in the incoming reference clock signal" which causes disruption (’827 Patent, col. 2:18-23). A party could argue that any phase error large or persistent enough to cause a "disruption" or an "out-of-lock" condition qualifies as a "step change."
  • Evidence for a Narrower Interpretation: The specification also discusses a step change in the context of switching from a primary to a secondary timing source, which implies an instantaneous or near-instantaneous event (’827 Patent, col. 8:51-54). A party could argue that an accumulation of "four or more consecutive...phase-errors" is a drift or frequency error, not the kind of abrupt "step change" the patent describes.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all three patents. It claims Defendant provides products with the capability to infringe and provides "documentation and training materials" (e.g., user manuals, product support) that "cause customers and end users" to operate the products in an infringing manner (Compl. ¶¶68, 97, 122). The complaint cites various datasheets as examples of this instructional material (Compl. ¶¶68, 97, 122, fns. 30-32).
• Willful Infringement: Willfulness is alleged for all three patents. The basis is primarily alleged post-suit knowledge, stating that "Cypress has had knowledge of the...Patent since at least service of this Complaint or shortly thereafter" (Compl. ¶¶67, 96, 121). The complaint also makes a general allegation that the patents are "well-known within the industry as demonstrated by multiple citations" as a basis for wanton or deliberate infringement (Compl. ¶¶69, 98, 123).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the behavior described in the accused products' datasheets—such as entering a "failsafe" mode upon "reference clock failure" or an "out-of-lock state" after accumulated phase errors—be construed to meet the specific claim limitations of "recentering a phase comparator" and detecting a "step change" as those terms are described in the patent specifications?
• A second key question will be evidentiary sufficiency: the complaint relies heavily on high-level functional descriptions and block diagrams from marketing datasheets. A central challenge for the plaintiff will be to demonstrate, with technical evidence beyond these documents, that the accused products' underlying hardware and software actually implement the specific methods and structures recited in the asserted claims.
• A final question relates to the patent-to-product mapping: the complaint asserts claim 21 of the '413 patent, which recites "step change" and "recenter" limitations, but the corresponding infringement narrative focuses on a different concept of "conditional holdover" based on quality levels. The case may turn on whether there is a fundamental mismatch between the specific claim asserted and the infringement theory presented for the '413 patent.