DCT

1:18-cv-00485

Godo Kaisha IP Bridge 1 v. Qualcomm Inc

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:18-cv-00485, D. Del., 05/25/2018
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because both Defendant entities are incorporated in Delaware and reside in the judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s Snapdragon semiconductor chips infringe eight patents related to semiconductor device structures and manufacturing methods, including technologies for managing physical stress, creating low-dielectric constant insulating layers, and fabricating device isolation structures.
  • Technical Context: The technologies at issue relate to fundamental techniques for improving performance and enabling miniaturization in advanced semiconductor manufacturing, which are critical for high-performance mobile processors.
  • Key Procedural History: The complaint alleges that Plaintiff IP Bridge and Defendant Qualcomm engaged in licensing discussions beginning with a letter from IP Bridge dated January 9, 2015. During these discussions, which included in-person meetings, Plaintiff allegedly identified the asserted patents and provided evidence of use presentations for certain patents, but the parties were unable to agree on license terms.

Case Timeline

Date Event
1995-07-27 Priority Date for ’409 and RE’980 Patents
1996-11-26 Priority Date for ’736 Patent
1999-01-27 Priority Date for ’824, ’802, and ’052 Patents
2000-10-02 Priority Date for ’677 Patent
2002-05-14 U.S. Patent No. 6,387,824 Issues
2002-09-12 U.S. Patent No. 6,346,736 Issues
2003-08-05 U.S. Patent No. 6,602,802 Issues
2004-09-21 U.S. Patent No. 6,794,677 Issues
2005-03-29 U.S. Patent No. 6,873,052 Issues
2005-11-22 U.S. Patent No. 6,967,409 Issues
2006-05-19 Priority Date for ’726 Patent
2010-12-07 U.S. Patent No. RE41,980 Issues
2013-01-15 U.S. Patent No. 8,354,726 Issues
2015-01-09 Plaintiff sends letter to Defendant identifying RE’980 Patent
2015-02-12 Defendant responds to Plaintiff's letter
2016-02-19 Plaintiff provides Defendant with evidence of use presentation for ’726 Patent
2016-03-30 Plaintiff and Defendant meet in person; Defendant allegedly has knowledge of all asserted patents except ’726 and RE’980 from this date
2018-03-30 Original Complaint filed
2018-05-25 First Amended Complaint filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,354,726 - “Semiconductor Device and Method for Fabricating the Same”

The Invention Explained

  • Problem Addressed: In advanced semiconductor manufacturing, mechanical stress applied to a transistor’s channel region by surrounding films can enhance or degrade carrier mobility, and thus device performance. The patent notes that an insulating film with internal stress, such as a silicon nitride liner, can be used to apply this stress, but its effects can be complex and counterproductive depending on the device layout (’726 Patent, col. 1:11-24).
  • The Patented Solution: The invention introduces an "auxiliary pattern" placed near the gate electrode of a transistor. This auxiliary pattern is also covered by the "stress-containing insulating film" that covers the main gate electrode (’726 Patent, col. 3:13-23). By carefully controlling the distance between the main gate and the auxiliary pattern, the invention claims to relieve unwanted compressive stress in the transistor's channel, thereby enhancing carrier mobility and improving performance (’726 Patent, col. 2:1-7; Fig. 1).
  • Technical Importance: This technique provides a method for strain engineering, a critical tool used in modern semiconductor nodes to boost transistor performance without shrinking feature sizes.

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶33).
  • Claim 1 recites a semiconductor device comprising:
    • A first active region on a semiconductor substrate.
    • A first gate electrode over the active region with a protrusion extending onto an isolation region.
    • A first side-wall insulating film on the side of the first gate electrode.
    • An auxiliary pattern spaced apart from the protrusion of the first gate electrode.
    • A second side-wall insulating film on the side of the auxiliary pattern.
    • A stress-containing insulating film covering the gate electrode, auxiliary pattern, and side-wall films.
    • A specific spatial relationship wherein the distance between the gate electrode and the auxiliary pattern is smaller than the sum of the thicknesses of the side-wall films and double the thickness of the stress-containing film.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 6,387,824 - “Method of Forming Porous Forming Film Wiring Structure”

The Invention Explained

  • Problem Addressed: As semiconductor wires (interconnects) are packed more closely together, the parasitic capacitance between them increases, leading to signal delays (RC delay) that limit the chip’s overall speed. To counteract this, insulating materials (inter-layer dielectrics) with a low dielectric constant (low-k) are needed (’824 Patent, col. 1:10-21). Creating porous films is a way to achieve very low-k values, but conventional methods were described as costly or complex (’824 Patent, col. 2:1-15).
  • The Patented Solution: The invention discloses a method to form a porous low-k dielectric film. The method begins by depositing an "organic-inorganic hybrid film" using plasma-enhanced chemical vapor deposition (PECVD) (’824 Patent, col. 5:5-12). After patterning and etching trenches for wires into this film, a plasma process with a reducing gas (such as hydrogen) is performed. This plasma process is claimed to simultaneously remove a photoresist mask and decompose the organic component within the hybrid film, leaving behind a porous structure with numerous fine holes (’824 Patent, col. 6:8-14; Fig. 3(c)).
  • Technical Importance: This method provides a potential pathway for integrating low-k dielectric materials into semiconductor manufacturing to reduce RC delay and improve high-frequency performance.

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶48).
  • Claim 1 recites a method for forming a wiring structure, comprising the steps of:
    • Depositing, on a substrate, an organic-inorganic hybrid film having a siloxane skeleton.
    • Forming a resist pattern on the hybrid film.
    • Etching the hybrid film using the resist pattern to form a depressed portion (e.g., a wire groove).
    • Performing a plasma process using a plasma from a reducing gas to remove the resist pattern and form an inter-layer dielectric which is a porous film.
    • Filling a metal film in the depressed portion to form a buried wire or contact.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 6,602,802 - “Method of Forming a Porous Film on a Substrate”

Technology Synopsis

This patent is related to the ’824 Patent and describes a method for forming a porous film. The method involves depositing an organic-inorganic hybrid film with a siloxane skeleton and then performing a process to decompose and eliminate the organic component, thereby creating a porous structure (’802 Patent, Abstract).

Asserted Claims

At least claim 1 (Compl. ¶59).

Accused Features

The complaint alleges that the method is used in the formation of porous film structures within the 28 nm Gate First, 28 nm Gate Last, and 40/45 nm Accused Products (Compl. ¶¶ 59-61). A visual in the complaint depicts this porous film. (Compl. ¶60; Exhibit H, First Am. Compl. Figs. 13-15).

U.S. Patent No. 6,967,409 - “Semiconductor Device and Method of Manufacturing the same”

Technology Synopsis

This patent describes a semiconductor device structure designed to improve integration density. The structure involves an isolation region that is higher than the active area, allowing a connection hole (or via) to be formed over both the active area and the isolation without requiring a large alignment margin, thereby saving space (’409 Patent, Abstract).

Asserted Claims

At least claim 1 (Compl. ¶69).

Accused Features

The complaint alleges that the 28 nm Gate First, 28 nm Gate Last, and 40/45 nm Accused Products embody this structure, specifically pointing to an interconnection formed on an isolation region with a stepped topography (Compl. ¶¶ 71-73).

U.S. Reissue Patent No. RE41,980 - “Semiconductor Interconnect Formed over an Insulation and having Moisture Resistant Material”

Technology Synopsis

This patent describes a structure for protecting metal wire layers from moisture. It uses a dual-layer surface protecting film, where a first dielectric film with a low dielectric constant fills areas between wires, and a second dielectric film with higher moisture resistance covers the first film and the wires. This structure aims to reduce parasitic capacitance while preventing moisture-related reliability issues (’RE980 Patent, Abstract).

Asserted Claims

At least claim 18 (Compl. ¶81).

Accused Features

The complaint alleges the Accused Products use this dual-layer protective film structure, with a low-k dielectric filling areas between metal wires and a second, moisture-resistant film covering it (Compl. ¶¶ 83-84).

U.S. Patent No. 6,794,677 - “Semiconductor Integrated Circuit Device and Method for Fabricating the Same”

Technology Synopsis

The patent addresses variations in pattern size during fabrication that arise from differences in pattern density across a chip. The solution involves inserting "dummy patterns" in less dense regions to equalize the total perimeter of linear patterns per unit area across the chip. This homogenization of pattern density is intended to improve manufacturing consistency and yield (’677 Patent, Abstract).

Asserted Claims

At least claim 1 (Compl. ¶93).

Accused Features

The Accused Products are alleged to use dummy patterns inserted into regions with less-repetitive circuit patterns to equalize the total pattern perimeter per unit area with that of regions having repetitive patterns (e.g., memory) (Compl. ¶¶ 95-97).

U.S. Patent No. 6,346,736 - “Trench Isolated Semiconductor Device”

Technology Synopsis

This patent describes a trench isolation structure aimed at reducing capacitance between wiring and the substrate to increase operating speed. The isolation region is composed of insulating trench portions and "dummy semiconductor portions." By forming a PN junction in these dummy portions, a capacitance component is added in series, which reduces the total wiring-to-substrate capacitance compared to a simple insulator (’736 Patent, Abstract).

Asserted Claims

At least claim 6 (Compl. ¶105).

Accused Features

The Accused Products are alleged to contain a structure with an active region, an isolation region with trench portions, and dummy semiconductor portions, along with a specific arrangement of insulating films, that infringes the patent (Compl. ¶¶ 107-109).

U.S. Patent No. 6,873,052 - “Porous, Film, Wiring Structure, and Method of Forming the same”

Technology Synopsis

This patent, related to the ’824 and ’802 patents, describes a wiring structure using multiple porous inter-layer dielectric films with different porosities. A first layer with lower porosity is used for contact holes, while a second layer with higher porosity is used for wire grooves. This dual-porosity approach aims to balance the need for low capacitance (high porosity) with mechanical stability (low porosity) (’052 Patent, Abstract).

Asserted Claims

At least claim 1 (Compl. ¶117).

Accused Features

The 28 nm Gate Last Accused Products are alleged to use a wiring structure with a first inter-layer dielectric of relatively low porosity and a second inter-layer dielectric of relatively high porosity (Compl. ¶¶ 119-120).

III. The Accused Instrumentality

Product Identification

The complaint identifies three categories of accused products:

  1. “40/45 nm Accused Products,” including the Qualcomm MSM8660 Snapdragon S3 (Compl. ¶13).
  2. “28 nm Gate First Accused Products,” including the Qualcomm MSM8960 Snapdragon S4 and MSM8916 Snapdragon 410 (Compl. ¶14).
  3. “28 nm Gate Last Accused Products,” including the Qualcomm MSM8974 Snapdragon 800 (Compl. ¶15).

Functionality and Market Context

  • The accused products are described as mobile application processors that integrate Qualcomm's Snapdragon processor technology (Compl. ¶34, ¶70). They are semiconductor chips fabricated using 45 nm, 40 nm, and 28 nm process nodes and are designed for use in consumer and enterprise electronic devices (Compl. ¶¶12-15).
  • The complaint alleges these products are essential components of the downstream devices into which they are integrated (Compl. ¶17). It further alleges that Qualcomm works closely with customers, OEMs, and foundry suppliers to design and manufacture these products for integration into a wide range of devices sold in the United States (Compl. ¶17, ¶19).

IV. Analysis of Infringement Allegations

’8,354,726 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a first active region (A) surrounded with an isolation region (G) of a semiconductor substrate The accused products are alleged to contain active regions surrounded by isolation regions. ¶35 col. 3:5-6
a first gate electrode (B) formed over the first active region and having a protrusion protruding on the isolation region The complaint alleges the presence of a gate electrode formed over the active region with a protrusion. The complaint references a visual that purportedly shows this structure. (Exhibit H, First Am. Compl. Figs. 1-2). ¶35 col. 3:7-10
a first side-wall insulating film (C) formed on the side surface of the first gate electrode The accused products are alleged to have a first side-wall insulating film on the gate electrode. The complaint references a visual that purportedly shows this structure. (Exhibit H, First Am. Compl. Figs. 3-4). ¶36 col. 3:11-12
an auxiliary pattern (D) formed over the semiconductor substrate to be spaced apart in the gate width direction from the protrusion of the first gate electrode An auxiliary pattern is allegedly formed on the substrate near the gate electrode protrusion. ¶37 col. 3:13-16
a second side-wall insulating film (E) formed on the side surface of the auxiliary pattern A second side-wall insulating film is allegedly formed on the side of the auxiliary pattern. The complaint references a visual that purportedly shows these structures. (Exhibit H, First Am. Compl. Figs. 5-8). ¶37 col. 3:17-18
a stress-containing insulating film (F) containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film The accused products allegedly include a stress-containing film covering the gate electrode, auxiliary pattern, and their respective side-wall films. ¶38 col. 3:19-23
wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of: the sum of the thicknesses of the first and second side-wall insulating films; and the double of the thickness of the stress-containing insulating film The complaint alleges that the physical arrangement of the gate electrode and auxiliary pattern in the accused products satisfies this specific dimensional relationship. ¶39 col. 3:24-30

Identified Points of Contention (’726 Patent)

  • Scope Questions: A central issue may be the construction of the term "auxiliary pattern." The analysis will question whether the structure identified in the accused products performs the stress-relieving function described in the patent, or if it is a standard design feature present for other reasons (e.g., pattern density uniformity).
  • Technical Questions: Infringement of the final limitation depends on precise physical measurements of the accused devices. A key question will be whether discovery and reverse engineering analysis confirm that the distance between the gate electrode and the alleged "auxiliary pattern" is smaller than the specified sum of film thicknesses.

’6,387,824 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
depositing, on a substrate, an organic-inorganic hybrid film having a siloxane skeleton The manufacturing process for the accused products allegedly involves depositing an organic silicate glass (OSG) film with a siloxane skeleton. ¶49 col. 5:5-12
forming a resist pattern on said organic-inorganic hybrid film This standard photolithography step is alleged to be part of the manufacturing process. ¶50 col. 5:66-67
performing etching with respect to the organic-inorganic hybrid film masked with said resist pattern to form a depressed portion composed of a wire groove (A) or a contact hole The process allegedly includes etching the hybrid film to create wire grooves or contact holes. ¶50 col. 6:3-7
performing a plasma process using a plasma derived from a gas containing a reducing gas with respect to said resist pattern and said organic-inorganic hybrid film to remove said resist pattern and form an inter-layer dielectric which is a porous film (C) The manufacturing process allegedly uses a plasma with reducing gases (e.g., Nitrogen, Ammonia) to remove the resist and simultaneously convert the hybrid film into a porous ultra-low k dielectric. The complaint references a visual showing the resulting structure. (Exhibit H, First Am. Compl. Figs. 13-15). ¶50 col. 6:8-14
filling a metal film in the depressed portion of said inter-layer dielectric to form a buried wire (B) or contact composed of said metal film The process allegedly concludes by filling the etched, porous dielectric with metal to form the interconnect wiring. ¶51 col. 6:15-18

Identified Points of Contention (’824 Patent)

  • Scope Questions: This being a method claim, infringement will turn on proving that the process used by Qualcomm's manufacturing partners (e.g., TSMC) includes the claimed steps. A key question will be whether the accused manufacturing flow uses a "plasma process... containing a reducing gas" for the specific dual purpose of removing resist and forming the porous film, as required by the claim.
  • Technical Questions: The complaint alleges the use of a "PECVD porogen approach" (Compl. ¶50). The analysis will question what evidence exists that this specific approach, as practiced by the foundries, maps onto all limitations of the claimed method, particularly the composition of the plasma and its dual function.

V. Key Claim Terms for Construction

For the ’726 Patent

  • The Term: "auxiliary pattern"
  • Context and Importance: The definition of this term is central to the infringement analysis. The complaint identifies a structure as the "auxiliary pattern," but the defense may argue this structure serves a different purpose and does not meet the claim's functional or structural requirements. Practitioners may focus on this term because its construction will determine whether common layout features in modern chip design fall within the scope of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not appear to limit the "auxiliary pattern" to any specific function other than being a physical structure placed at a specific distance from the gate electrode and covered by the stress film. The specification states it is "spaced apart in the gate width direction from the protrusion of the first gate electrode" (’726 Patent, col. 3:13-16), a purely structural definition.
    • Evidence for a Narrower Interpretation: The patent's objective is to relieve compressive stress (’726 Patent, col. 2:1-7). A defendant may argue that for a structure to be an "auxiliary pattern," it must be shown to contribute to this stress-relieving function in the manner described, rather than just being a geometrically-proximate feature.

For the ’824 Patent

  • The Term: "performing a plasma process using a plasma derived from a gas containing a reducing gas...to remove said resist pattern and form an inter-layer dielectric which is a porous film"
  • Context and Importance: This limitation recites a single process step with a dual function: resist removal and porous film formation. The case will likely hinge on whether the manufacturing process for the accused products performs these two functions in the claimed manner using a single plasma process. Practitioners may focus on this term because it links two distinct manufacturing outcomes to a single technological step, creating a specific sequence and mechanism that may not be present in all low-k fabrication methods.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language does not specify the exact chemistry of the reducing gas or the precise mechanism of pore formation, only that a plasma with a reducing gas achieves the dual result. The specification mentions that as a result of the plasma process, "an organic component...eliminates therefrom and numerous fine holes are formed" (’824 Patent, col. 1:40-45), suggesting the outcome is the key.
    • Evidence for a Narrower Interpretation: A defendant may argue that the claim requires the same plasma process to be responsible for both stripping the resist and creating the pores. If the accused process uses separate steps (e.g., a primary resist strip followed by a different curing or plasma treatment to create porosity), it may not meet this limitation. The patent's abstract distinguishes its method by stating the organic component "eliminates therefrom," which could be argued to imply a specific subtractive mechanism tied to the plasma step.

VI. Other Allegations

Indirect Infringement

The complaint alleges induced infringement for all asserted patents. The basis for inducement is that Qualcomm allegedly "encourages, trains, instructs, and provides support and technical assistance to others" (e.g., foundry suppliers and customers) to infringe (Compl. ¶¶ 41, 52). Specific alleged acts include contracting with foundries to manufacture the accused products and publishing technical materials, product specifications, and development resources (e.g., MDPs, QDN tools) that instruct customers on how to integrate the accused products (Compl. ¶¶ 41, 52, 62, 74, 86, 98, 110, 122).

Willful Infringement

The complaint alleges willful infringement for all asserted patents. Willfulness is primarily based on alleged pre-suit knowledge. Plaintiff alleges sending a letter identifying the RE’980 patent on January 9, 2015, and providing an evidence-of-use presentation for the ’726 patent on February 19, 2016 (Compl. ¶¶ 24, 32, 80). For the remaining six patents, knowledge is alleged from "at least as early as March 30, 2016," the date of an in-person meeting (Compl. ¶¶ 47, 58, 68, 92, 104, 116). Willfulness is also alleged based on knowledge from the filing of the original complaint on March 30, 2018 (e.g., Compl. ¶32).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of claim scope and function: Can the term “auxiliary pattern” in the ’726 patent be construed to cover structures in the accused devices that may be present for reasons unrelated to stress engineering, or must the pattern be shown to actively perform the stress-relieving function described in the patent?
  • A key evidentiary question will be one of process mapping: For the method patents (’824, ’802), what evidence can be obtained from third-party foundries to demonstrate that their proprietary manufacturing flows perform the specific, multi-function process steps—such as using a single reducing-gas plasma to both strip resist and create film porosity—as required by the asserted claims?
  • A central question across the portfolio will be technological equivalence: Do the asserted patents, many with priority dates from the late 1990s and early 2000s, claim structures and methods that are fundamental building blocks of modern 45/40/28 nm manufacturing, or have the accused processes evolved in ways that are technically distinct from the specific embodiments disclosed and claimed in the patents?