DCT

1:18-cv-00485

Godo Kaisha IP Bridge 1 v. Qualcomm Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:18-cv-00485, D. Del., 03/30/2018
  • Venue Allegations: Venue is alleged to be proper as both Defendants are Delaware corporations and are therefore residents of the judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s Snapdragon semiconductor chips infringe seven patents related to semiconductor device structures, fabrication methods, and materials.
  • Technical Context: The patents relate to advanced semiconductor manufacturing techniques, including stress engineering, low-k dielectrics, and pattern uniformity control, which are critical for enhancing the performance and reducing the size of modern processors.
  • Key Procedural History: The complaint alleges that Plaintiff and Defendant engaged in licensing discussions beginning on January 9, 2015, during which Plaintiff identified at least some of the asserted patents and provided evidence of use presentations. The '677' Patent is also being asserted by Plaintiff against a third party in a separate action in the same district.

Case Timeline

Date Event
1996-11-26 Priority Date ('736' Patent)
1999-01-27 Priority Date ('824' Patent, '802' Patent)
2000-10-02 Priority Date ('677 Patent)
2002-05-14 Issue Date ('824 Patent)
2002-09-12 Issue Date ('736 Patent)
2003-08-05 Issue Date ('802 Patent)
2004-09-21 Issue Date ('677 Patent)
2005-11-22 Issue Date ('409' Patent)
2006-05-19 Priority Date ('726' Patent, '409 Patent, RE'980' Patent)
2010-12-07 Issue Date (RE'980 Patent)
2013-01-15 Issue Date ('726 Patent)
2015-01-09 Plaintiff allegedly provides notice of RE'980 Patent to Defendant
2015-02-12 Defendant allegedly responds to Plaintiff's notice
2016-02-19 Plaintiff allegedly provides evidence of use presentation for '726 Patent to Defendant
2016-03-30 Plaintiff and Defendant allegedly meet; alleged notice date for '824, '802, '409, '677, '736 Patents
2018-03-30 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,354,726 - "Semiconductor Device and Method for Fabricating the Same," issued January 15, 2013

The Invention Explained

  • Problem Addressed: The patent describes the challenge of increasing transistor performance as device dimensions shrink. A key method to boost performance is to apply mechanical stress to the transistor's channel region to improve carrier mobility. ('726 Patent, col. 1:25-33).
  • The Patented Solution: The invention proposes a specific device structure to control and enhance this stress effect. It involves placing an "auxiliary pattern" near the primary gate electrode and covering both with a "stress-containing insulating film." ('726 Patent, Abstract). The precise spacing and dimensions of these elements are claimed to optimize the stress applied to the channel, thereby improving device performance. ('726 Patent, col. 2:1-15).
  • Technical Importance: Applying mechanical strain to silicon is a fundamental technique used in advanced semiconductor nodes to counteract performance degradation from miniaturization and continue the trend of Moore's Law. ('726 Patent, col. 1:25-33).

Key Claims at a Glance

  • The complaint asserts independent Claim 1. (Compl. ¶32).
  • Essential elements of Claim 1 include:
    • A first active region on a semiconductor substrate surrounded by an isolation region.
    • A first gate electrode over the active region with a protrusion onto the isolation region.
    • A first side-wall insulating film on the side of the first gate electrode.
    • An auxiliary pattern spaced apart from the gate electrode's protrusion.
    • A second side-wall insulating film on the side of the auxiliary pattern.
    • A stress-containing insulating film covering these components.
    • A specific geometric requirement that the distance between the gate electrode and the auxiliary pattern is smaller than the sum of the thicknesses of the sidewall films and double the thickness of the stress film.
  • The complaint reserves the right to assert additional claims. (Compl. ¶32).

U.S. Patent No. 6,387,824 - "Method of Forming Porous Forming Film Wiring Structure," issued May 14, 2002

The Invention Explained

  • Problem Addressed: The patent addresses "wiring delay time" in integrated circuits, which is caused by parasitic capacitance between closely spaced metal wires. This RC delay is a significant bottleneck for achieving higher performance in modern chips. ('824 Patent, col. 1:8-17).
  • The Patented Solution: The invention is a method for creating a porous inter-layer dielectric film with a low dielectric constant (low-k) to reduce this capacitance. The method involves depositing an "organic-inorganic hybrid film" (having a siloxane skeleton) and then performing a plasma process with a "reducing gas" (e.g., hydrogen). ('824 Patent, Abstract). This plasma process removes the organic component, leaving behind numerous fine holes or pores, thereby lowering the film's overall dielectric constant. ('824 Patent, col. 1:35-43).
  • Technical Importance: The use of low-k and ultra-low-k dielectric materials in the interconnect structure is a critical enabling technology for manufacturing high-speed processors at advanced process nodes. ('824 Patent, col. 1:20-24).

Key Claims at a Glance

  • The complaint asserts independent Claim 1. (Compl. ¶47).
  • Essential elements of Claim 1, a method claim, include the steps of:
    • Depositing, on a substrate, an organic-inorganic hybrid film having a siloxane skeleton.
    • Forming a resist pattern on the hybrid film.
    • Etching the hybrid film to form a depressed portion (e.g., a wire groove).
    • Performing a plasma process with a plasma derived from a reducing gas to remove the resist and form a porous inter-layer dielectric from the hybrid film.
    • Filling the depressed portion with a metal film to form a buried wire.
  • The complaint reserves the right to assert additional claims. (Compl. ¶47).

U.S. Patent No. 6,602,802 - "Method of Forming a Porous Film on a Substrate," issued August 5, 2003

  • Patent Identification: 6,602,802, "Method of Forming a Porous Film on a Substrate," issued August 5, 2003. (Compl. ¶55).
  • Technology Synopsis: Similar to the '824 Patent, this patent discloses a method for creating a low-k dielectric film. The method involves depositing an organic-inorganic hybrid film and subsequently performing a process to remove the organic component, thereby creating a porous structure to reduce parasitic capacitance. ('802 Patent, Abstract).
  • Asserted Claims: At least Claim 1 is asserted. (Compl. ¶58).
  • Accused Features: The method of forming the porous inter-layer dielectric films in the Accused Semiconductor Products. (Compl. ¶¶59-60).

U.S. Patent No. 6,967,409 - "Semiconductor Device and Method of Manufacturing the same," issued November 22, 2005

  • Patent Identification: 6,967,409, "Semiconductor Device and Method of Manufacturing the same," issued November 22, 2005. (Compl. ¶65).
  • Technology Synopsis: This patent describes a semiconductor device structure for forming connections (contacts) between different layers. The invention specifies a particular topography where the top surface of an isolation region connected to a conductive layer is at a lower level than another part of the isolation region, a structure designed to improve manufacturing reliability and device integration. ('409 Patent, Abstract). The complaint references visuals showing an isolation layer, interconnection, and a conductive layer formed in a hole. (Compl. ¶¶70-72; Exhibit H, Compl. Figs. 16-18).
  • Asserted Claims: At least Claim 1 is asserted. (Compl. ¶68).
  • Accused Features: The interconnect structures that connect active regions on the substrate to other layers in the Accused Semiconductor Products. (Compl. ¶¶70-72).

U.S. Patent No. RE41,980 - "Semiconductor Interconnect Formed over an Insulation and having Moisture Resistant Material," issued December 7, 2010

  • Patent Identification: RE41,980, "Semiconductor Interconnect Formed over an Insulation and having Moisture Resistant Material," issued December 7, 2010. (Compl. ¶77).
  • Technology Synopsis: This patent discloses a structure for protecting the final metal wire layer of a semiconductor device. The solution involves a multi-layer surface protecting film, where a first dielectric film has a low dielectric constant (to reduce capacitance) and a second dielectric film has high moisture resistance to protect the underlying layers, particularly around bonding pads where the chip connects to the outside world. (RE'980 Patent, Abstract).
  • Asserted Claims: At least Claim 18 is asserted. (Compl. ¶80).
  • Accused Features: The surface protecting films and bonding pad structures of the Accused Semiconductor Products. (Compl. ¶¶82-84).

U.S. Patent No. 6,794,677 - "Semiconductor Integrated Circuit Device and Method for Fabricating the Same," issued September 21, 2004

  • Patent Identification: 6,794,677, "Semiconductor Integrated Circuit Device and Method for Fabricating the Same," issued September 21, 2004. (Compl. ¶89).
  • Technology Synopsis: This patent addresses the problem of manufacturing variations caused by non-uniform pattern density across a chip. The invention proposes inserting non-functional "dummy patterns" into regions with sparse circuitry to make the overall pattern density more uniform, thereby improving the consistency of fabrication processes like etching and polishing. ('677 Patent, Abstract). The complaint provides visuals illustrating a first circuit pattern with a repetitive structure and a second, different circuit pattern with inserted dummy patterns. (Compl. ¶¶94-96; Exhibit H, Compl. Figs. 32-34).
  • Asserted Claims: At least Claim 1 is asserted. (Compl. ¶92).
  • Accused Features: The use of dummy patterns in regions of the Accused Semiconductor Products that contain components other than repetitive element groups (e.g., in logic areas adjacent to memory areas). (Compl. ¶¶94-96).

U.S. Patent No. 6,346,736 - "Trench Isolated Semiconductor Device," issued September 12, 2002

  • Patent Identification: 6,346,736, "Trench Isolated Semiconductor Device," issued September 12, 2002. (Compl. ¶101).
  • Technology Synopsis: This patent discloses a device structure designed to reduce the wiring-to-substrate capacitance in trench-isolated devices. The invention focuses on the structure of the isolation region itself, which is composed of trench portions and "dummy semiconductor portions," claiming that specific dielectric film arrangements within this isolation region can lower the total capacitance and increase operating speed. ('736 Patent, Abstract).
  • Asserted Claims: At least Claim 6 is asserted. (Compl. ¶104).
  • Accused Features: The structure of the trench isolation regions, including active regions, isolation regions, trenches, and interlayer insulating films in the Accused Semiconductor Products. (Compl. ¶¶106-108).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies three categories of accused products: "40/45 nm Accused Products," including the MSM8660 Snapdragon S3; "28 nm Gate First Accused Products," including the MSM8960 Snapdragon S4; and "28 nm Gate Last Accused Products," including the MSM8974 Snapdragon 800. (Compl. ¶¶13-16).

Functionality and Market Context

  • The accused products are identified as semiconductor chips, specifically mobile applications processors that integrate Snapdragon processors. (Compl. ¶¶13-15). The complaint alleges these chips are integrated into devices sold by original equipment manufacturers ("OEMs"), original design manufacturers ("ODMs"), and others, and are essential components of those end products. (Compl. ¶17).

IV. Analysis of Infringement Allegations

'726 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a first active region surrounded with an isolation region of a semiconductor substrate; and a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region The accused products allegedly comprise an active region (A) on a substrate, surrounded by an isolation region (G), with a gate electrode (B) formed over it that protrudes onto the isolation region. A visual from a sealed exhibit allegedly shows this structure. ¶34 col. 4:6-14
a first side-wall insulating film formed on the side surface of the first gate electrode The accused products allegedly have a first side-wall insulating film (C) on the side of the gate electrode. ¶35 col. 4:15-17
an auxiliary pattern formed over the semiconductor substrate to be spaced apart in the gate width direction from the protrusion of the first gate electrode; and a second side-wall insulating film formed on the side surface of the auxiliary pattern The accused products allegedly include an auxiliary pattern (D) spaced from the gate electrode protrusion, with a second side-wall insulating film (E) on its surface. ¶36 col. 4:18-24
a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film The accused products allegedly have a stress-containing insulating film (F) that covers the gate electrode, sidewalls, and auxiliary pattern. ¶37 col. 4:25-30
wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of: the sum of the thicknesses of the first and second side-wall insulating films; and the double of the thickness of the stress-containing insulating film The accused products are allegedly arranged such that the distance between the gate electrode and auxiliary pattern satisfies this specific geometric inequality. ¶38 col. 4:31-38

Identified Points of Contention

  • Scope Questions: A central point of contention may be the construction of "auxiliary pattern." The dispute could turn on whether any nearby conductive structure qualifies, or if the term is limited to specific structures disclosed in the patent's embodiments for the sole purpose of stress modulation.
  • Technical Questions: A key factual question will be whether the specific dimensional relationships required by the final limitation of Claim 1 are met in the accused products. This will likely require expert analysis of the physical chip structure to verify if the distance between the gate and auxiliary pattern is indeed smaller than the complex sum of other film thicknesses.

'824 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
depositing, on a substrate, an organic-inorganic hybrid film having a siloxane skeleton The manufacturing process for the accused products allegedly includes depositing an organic-inorganic hybrid film with a siloxane skeleton, such as organic silicate glass (OSG). ¶48 col. 5:5-10
forming a resist pattern on said organic-inorganic hybrid film; performing etching...to form a depressed portion composed of a wire groove (A) or a contact hole The process allegedly involves masking and etching the hybrid film to form grooves or holes for wiring. ¶49 col. 5:11-17
performing a plasma process using a plasma derived from a gas containing a reducing gas with respect to said resist pattern and said organic-inorganic hybrid film to remove said resist pattern and form an inter-layer dielectric which is a porous film (C) The process allegedly uses a plasma with a reducing gas (e.g., nitrogen, ammonia) to remove the resist and simultaneously convert the hybrid film into a porous, low-k dielectric film (C). A visual from a sealed exhibit allegedly shows this porous film. ¶49 col. 5:18-27
filling a metal film in the depressed portion of said inter-layer dielectric to form a buried wire (B) or contact composed of said metal film The process allegedly concludes by filling the etched grooves in the porous dielectric with metal to form buried wires (B). ¶50 col. 5:28-31

Identified Points of Contention

  • Evidentiary Questions: As this is a method patent asserted against a fabless semiconductor company, a primary issue will be proving the specific steps performed by Defendant's third-party foundry suppliers. The complaint relies on analysis of the final product structure, but the core of the claim lies in the process used to create that structure. The central evidentiary question will be what proof exists that the foundries use a "plasma process" with a "reducing gas" to create porosity, as opposed to other known methods for forming low-k films.
  • Scope Questions: The construction of "reducing gas" may be a point of dispute. The patent provides examples, and the infringement analysis will depend on whether the gases used in the actual manufacturing process fall within the claim's scope as it is ultimately construed.

V. Key Claim Terms for Construction

For the '726 Patent

  • The Term: "auxiliary pattern"
  • Context and Importance: The definition of this term is critical to determining the scope of Claim 1. Practitioners may focus on this term because its identity—whether it can be any nearby conductive line or must be a non-functional structure added specifically for stress engineering—will determine if the claim reads on standard logic layouts or is confined to more specialized configurations.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent states the auxiliary pattern is formed "to be spaced apart in the gate width direction from the protrusion of the first gate electrode," without limiting its function, which may support a broader reading on any appropriately positioned structure. ('726 Patent, col. 4:18-22).
    • Evidence for a Narrower Interpretation: The detailed description and figures consistently depict the auxiliary pattern as a structure that mirrors the gate electrode but is not part of an active transistor, suggesting its primary or sole purpose is related to stress mechanics, which may support a narrower construction. ('726 Patent, Fig. 1A).

For the '824 Patent

  • The Term: "organic-inorganic hybrid film having a siloxane skeleton"
  • Context and Importance: This term defines the starting material for the claimed method. The infringement case depends on whether the material deposited by the accused manufacturing process meets this definition. Practitioners may focus on this term because various precursors can be used in modern deposition processes, and the dispute may turn on the precise chemical composition of the film before it is made porous.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the film broadly, stating that plasma enhanced CVD using "a gas mixture of a silicon alkoxide and an organic compound" can be used to deposit it, suggesting a range of possible compositions. ('824 Patent, col. 1:35-39).
    • Evidence for a Narrower Interpretation: The patent’s examples and figures describe the film in the context of specific materials like "organic silicate glass (OSG)," which could be argued to limit the scope to films with that particular character. ('824 Patent, Fig. 1).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges active inducement of infringement for all asserted patents. The factual basis for inducement includes allegations that Defendant contracts with and instructs foundry suppliers (e.g., TSMC) to manufacture the accused chips using the patented methods and structures. (Compl. ¶¶40, 51). Further, it is alleged that Defendant encourages and provides technical support (e.g., through its Qualcomm Developer Network) to OEMs and other third parties to integrate these infringing chips into end products. (Compl. ¶¶40, 51).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents based on alleged pre-suit knowledge. Knowledge of the RE'980 Patent is alleged as of January 9, 2015, based on a letter from Plaintiff. (Compl. ¶79). Knowledge of the '726 Patent is alleged as of February 19, 2016, based on an evidence-of-use presentation. (Compl. ¶31). Knowledge for the remaining five patents is alleged as of March 30, 2016, a date associated with an in-person meeting. (Compl. ¶¶46, 57, 67, 91, 103).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of evidentiary proof for method claims: For the patents claiming a method of manufacturing (e.g., '824, '802), what discovery evidence will establish the precise steps, materials, and process gases used by Defendant's third-party foundries, and does that evidence map to the specific process limitations recited in the claims?
  • A key legal question will be one of claim scope for device claims: Can terms describing specific semiconductor structures, such as the "auxiliary pattern" ('726 Patent) and "dummy pattern" ('677 Patent), be construed to cover features in complex, multi-purpose processors that may have existed for other design reasons, or are the claims limited to structures implemented for the specific purpose disclosed in the patents?
  • A central question for damages will be one of knowledge and intent: Given the complaint's detailed allegations of pre-suit notice and licensing negotiations, the court will need to determine whether Defendant's conduct after being put on notice of the patents and infringement allegations was objectively reckless, which could support a finding of willful infringement and lead to enhanced damages.