DCT

1:18-cv-00925

DIFF Scale Operation Research LLC v. NXP USA Inc

Log In
Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:18-cv-00925, E.D. Tex., 03/13/2018
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants have transacted business in the Eastern District of Texas, committed acts of infringement in the district, and maintain offices and facilities within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s microcontrollers, processors, and RF transceivers infringe five patents related to semiconductor timing circuits, adaptive clock recovery, and network traffic shaping.
  • Technical Context: The patents relate to foundational technologies for ensuring precise timing and managing data flow in complex semiconductor devices, which are critical functions in modern telecommunications infrastructure and electronics.
  • Key Procedural History: The complaint notes that the asserted patent portfolio originated with ADC Telecommunications, Inc. and was part of a larger portfolio sold to HTC for $75 million in 2011. The complaint highlights that patents from this portfolio were previously asserted by HTC against Apple in the International Trade Commission, suggesting a history of valuation and assertion. CommScope, Inc. later acquired ADC Telecommunications and assigned the patents-in-suit to the Plaintiff to facilitate licensing.

Case Timeline

Date Event
1998-02-20 ’983 Patent Priority Date
1999-11-19 ’328 Patent Priority Date
2001-03-02 ’413 Patent Priority Date
2001-03-02 ’827 Patent Priority Date
2001-08-03 ’758 Patent Priority Date
2002-06-18 ’983 Patent Issue Date
2003-12-16 ’827 Patent Issue Date
2004-04-13 ’328 Patent Issue Date
2006-09-12 ’758 Patent Issue Date
2011-02-01 ’413 Patent Issue Date
2018-03-13 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,881,413 - “Digital PLL With Conditional Holdover”

  • Issued: February 1, 2011

The Invention Explained

  • Problem Addressed: High-reliability communication systems depend on stable timing signals derived from a reference clock. If this reference clock fails or its quality degrades, it can disrupt the entire network and cause data loss (’413 Patent, col. 2:4-14). The technical challenge is to maintain a stable timing signal even when the primary reference source becomes unreliable.
  • The Patented Solution: The invention describes a phase-locked loop (PLL) that intelligently decides when to trust its reference clock. It monitors a "status message" (like a Synchronization Status Message, or SSM) that indicates the quality of the incoming clock signal (’413 Patent, col. 4:20-25). If the quality drops below a predetermined target level, the PLL enters a "conditional holdover" mode, disconnecting from the faulty input and generating its own stable timing signal based on its last known good state, thereby preventing errors from propagating through the network (’413 Patent, Abstract).
  • Technical Importance: This technology allows network equipment to maintain operational stability during timing source failures, a critical requirement for carrier-grade telecommunications networks that demand high uptime and data integrity (Compl. ¶38).

Key Claims at a Glance

  • The complaint asserts at least independent claim 21 (Compl. ¶91).
  • Essential elements of a system according to claim 21, as characterized by the complaint’s allegations, include:
    • A system for generating a timing signal from a reference clock signal in a phase locked loop (Compl. ¶87).
    • Functionality for monitoring a status message received from the source of the reference clock signal, where the message is indicative of the signal’s quality level (Compl. ¶88).
    • Functionality for placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level (Compl. ¶89).

U.S. Patent No. 6,664,827 - “Direct Digital Synthesizer Phase Locked Loop”

  • Issued: December 16, 2003

The Invention Explained

  • Problem Addressed: Conventional PLLs can be disrupted by a sudden "step change" in the phase of an incoming reference clock, which often occurs when a system switches between primary and backup timing sources. This disruption can cause the PLL’s output to become unstable until it reacquires lock (’827 Patent, col. 2:18-23). Additionally, the oscillators within PLLs are prone to long-term frequency drift.
  • The Patented Solution: The patent discloses a digital PLL that uses a processor to actively monitor for such step changes. Upon detecting a step change, the system can "recenter" its digital phase comparator, allowing it to mitigate the disruption and maintain a stable output signal (’827 Patent, col. 2:57-62). The invention also describes a method for compensating for long-term oscillator drift by sampling an average control signal and trimming the oscillator if the average deviates beyond a threshold limit (’827 Patent, Abstract).
  • Technical Importance: This approach enhances the robustness of timing circuits, making them less susceptible to instability caused by network events like switching reference clocks, which is crucial for maintaining synchronization in complex communication systems (Compl. ¶41).

Key Claims at a Glance

  • The complaint asserts at least independent claim 28 (Compl. ¶117).
  • Essential elements of the method of claim 28 include:
    • Sampling values of an error signal indicative of a phase relationship between a reference clock signal and a feedback signal.
    • Monitoring the sampled error signal values for a step change in the phase difference.
    • Recentering a phase comparator if a step change in the phase difference is detected.
  • The complaint does not explicitly reserve the right to assert dependent claims for the ’827 Patent.

U.S. Patent No. 7,106,758 - “Circuit and Method for Service Clock Recovery”

  • Issued: September 12, 2006 (Compl. ¶47)
  • Technology Synopsis: The patent addresses clock synchronization in a packet network where a destination node must recover the service clock of a source node (Compl. ¶48). The invention uses an adaptive clock recovery technique where a local clock is controlled based on values, such as buffer fill levels, calculated over a plurality of time periods to ensure synchronization (Compl. ¶¶52, 54).
  • Asserted Claims: At least claim 40 (Compl. ¶144).
  • Accused Features: The accused features relate to clock recovery technology in Defendant's SC28L194A1A and SC28L194A1BE Quad UART products (Compl. ¶¶127, 129).

U.S. Patent No. 6,407,983 - “Circuit and Method for Shaping Traffic in a Virtual Connection Network”

  • Issued: June 18, 2002 (Compl. ¶56)
  • Technology Synopsis: The patent describes a system and method for "traffic shaping," which smooths out "bursty" data traffic to deliver data packets at a substantially uniform rate (Compl. ¶¶57, 58). The invention uses a request generator that strategically requests timeslots for data transmission from a buffer to evenly distribute the requests over a measurement window, thereby achieving a desired data rate (Compl. ¶¶57, 59).
  • Asserted Claims: At least claim 8 (Compl. ¶163).
  • Accused Features: The accused features relate to traffic shaping technology in Defendant's QorIQ T4 family of processors (Compl. ¶¶153, 155).

U.S. Patent No. 6,721,328 - “Adaptive Clock Recovery for Circuit Emulation Service”

  • Issued: April 13, 2004 (Compl. ¶66)
  • Technology Synopsis: This patent discloses a system for adaptive clock recovery in a packet network. The invention monitors the fill level of a data buffer and identifies a "relative maximum fill level" over a period of time (Compl. ¶67). This maximum fill level is then used to control the frequency of a locally generated clock, thereby controlling the rate at which data is read out of the buffer and synchronizing the local clock with the source clock (Compl. ¶67).
  • Asserted Claims: At least claim 1 (Compl. ¶182).
  • Accused Features: The accused features relate to clock recovery technology in Defendant's SC28L194A1A and SC28L194A1BE Quad UART products (Compl. ¶¶168, 170).

III. The Accused Instrumentality

Product Identification

  • The complaint accuses multiple product families, including the S12XE, S12P, S12XS, S12NE, and MAC7100 series of microcontrollers; the OL23xx series of RF transceivers and receivers; the SC28L194 series of Quad UARTs; and the QorIQ T4 family of multicore communications processors (Compl. ¶¶77, 100, 127, 153, 168).

Functionality and Market Context

  • The accused microcontrollers and RF products are alleged to incorporate phase-locked loop (PLL) timing circuits for generating timing signals from a reference clock (Compl. ¶¶76, 79). The complaint includes a datasheet diagram illustrating a "Basic PLL Functional Diagram" for the MAC7100 family, showing a phase detector, loop filter, and voltage-controlled oscillator (VCO) in a feedback arrangement (Compl. p. 25, Figure 3).
  • The complaint alleges the Quad UART products implement adaptive clock recovery by receiving serial data, storing it in a receiver buffer memory (FIFO), monitoring the FIFO's fill level, and using a local clock to read out the data (Compl. ¶¶133, 135-137). A datasheet excerpt describes the "Receiver FIFO" as a 16-byte buffer memory (Compl. p. 36).
  • The QorIQ processors are alleged to perform traffic shaping. A presentation slide titled "Queuing Structure" is provided to illustrate the products' technology for controlling data traffic, showing frame descriptors, frame queues, and work queues used to manage data flows (Compl. p. 41). The complaint alleges these products are sold for use in the United States (Compl. ¶76).

IV. Analysis of Infringement Allegations

’413 Patent Infringement Allegations

Claim Element (from Independent Claim 21, as alleged) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for generating a timing signal from a reference clock signal in a phase locked loop The accused NXP products are alleged to comprise a system for generating a timing signal in a PLL, as shown in product datasheets. ¶87 col. 2:25-30
Functionality for monitoring a status message received from a source of the reference clock signal indicative of a quality level The accused products allegedly feature a "clock monitor" that asserts a "Clock Monitor Failure" if the incoming clock frequency falls below a specific threshold. ¶88 col. 4:20-25
Functionality for placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level The complaint alleges that upon detection of a clock failure, the accused products switch to an "internal self clock mode," which it characterizes as the claimed holdover condition. ¶89 col. 4:32-36
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the accused "Clock Monitor Failure" signal, which appears to indicate a binary frequency failure, constitutes a "status message indicative of a quality level" as that term is used in the patent. The patent specification discusses standardized, multi-level Synchronization Status Messages (SSMs), raising the question of whether a simple failure alert falls within the claim's scope (’413 Patent, col. 2:35-41).
    • Technical Questions: The complaint alleges that switching to an "internal self clock mode" is equivalent to the claimed "holdover condition." The analysis may turn on whether this internal mode operates based on the PLL's last known good state, as described in the patent, or if it is a fundamentally different type of backup clock operation.

’827 Patent Infringement Allegations

Claim Element (from Independent Claim 28) Alleged Infringing Functionality Complaint Citation Patent Citation
sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal The accused products allegedly measure the deviation from the reference clock with each transition of the comparison clock and adjust the VCO voltage accordingly. ¶113 col. 10:55-58
monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal The complaint alleges, without specific supporting evidence from product documentation, that the accused products include infringing technology for monitoring for a step change. ¶114 col. 12:4-14
recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected The complaint alleges, without specific supporting evidence from product documentation, that the accused products include functionality for recentering the phase comparator upon detection of a step change. ¶116 col. 12:39-44
  • Identified Points of Contention:
    • Technical Questions: While the complaint provides evidence that the accused PLLs measure phase deviation (a standard function), it does not provide direct evidence of the specific claimed functions of "monitoring... for a step change" and actively "recentering" the comparator. A key dispute may be whether the normal, continuous error correction of the accused PLL feedback loop is functionally equivalent to the discrete detection-and-correction method claimed in the patent.

V. Key Claim Terms for Construction

For the ’413 Patent:

  • The Term: "status message indicative of a quality level"
  • Context and Importance: This term is critical, as infringement hinges on whether the accused "Clock Monitor Failure" signal meets this limitation. Practitioners may focus on this term because the patent’s context suggests a structured, multi-level quality indicator, while the accused feature appears to be a binary failure flag.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not specify a particular format for the "status message," which may support an argument that any signal conveying information about the clock's quality or failure state is sufficient.
    • Evidence for a Narrower Interpretation: The specification explicitly references "Synchronization Status Message (SSM) of Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) formats" as an example, which could support an argument that the term is limited to standardized, multi-bit messages that convey distinct quality levels, not just a simple failure alarm (’413 Patent, col. 2:35-41).

For the ’827 Patent:

  • The Term: "recenter the digital phase comparator"
  • Context and Importance: The act of "recentering" is a core part of the patented solution to handling phase step changes. The dispute will likely center on whether this requires a specific, discrete action separate from the normal operation of a PLL, or if the continuous self-correction of any PLL can be characterized as "recentering."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The summary of the invention describes the processor's function as to "recenter the digital phase comparator if a step change is detected," which may support a functional interpretation covering any corrective action that mitigates the step change (’827 Patent, col. 2:61-62).
    • Evidence for a Narrower Interpretation: A specific embodiment describes recentering by "monitoring and adjusting divide-by-N counters of the frequency dividers," suggesting a specific structural implementation rather than just any functional adjustment (’827 Patent, col. 12:39-50).

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement. It claims NXP provides "documentation and training materials," including user manuals and datasheets, that instruct customers and end-users to operate the accused products in a manner that directly infringes (Compl. ¶¶94, 121, 147, 185).
  • Willful Infringement: The complaint alleges willful infringement. For the ’413 patent, it bases this on knowledge acquired at least from the service of the complaint (Compl. ¶93). For the ’827 patent, it makes a similar post-suit allegation but also alleges pre-suit knowledge since at least December 2015, based on a citation to the ’827 patent in U.S. Patent No. 7,420,426, which NXP acquired from Freescale Semiconductor (Compl. ¶¶119-120).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: For the ’413 patent, can a binary "clock monitor failure" alarm in a microcontroller be construed to meet the "status message indicative of a quality level" limitation, a term rooted in the context of multi-level telecommunication standards like SONET/SDH?
  • A key evidentiary question will be one of functional distinction: For the ’827 patent, does the accused PLL’s standard feedback mechanism perform the specific, discrete steps of "monitoring for a step change" and "recentering" the comparator as claimed, or is there a fundamental mismatch between the continuous self-correction of the accused device and the event-driven intervention described in the patent?
  • The allegation of pre-suit knowledge for the ’827 patent, based on a citation in NXP's own acquired patent portfolio, will be a critical issue for willfulness. The case may explore whether such a citation can be imputed as the requisite knowledge to the accused infringer to support a finding of willful infringement prior to the lawsuit's filing.