VLSI Technology LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: VLSI Technology LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff’s Counsel: Farnan LLP
• Case Identification: 1:18-cv-00966, D. Del., 06/28/2018
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Intel Corporation is incorporated in Delaware.
• Core Dispute: Plaintiff alleges that Defendant’s microprocessors and related chipset technologies infringe five patents related to on-chip communication security, dynamic power optimization, semiconductor manufacturing methods, low-power state management, and power-gating control.
• Technical Context: The dispute centers on fundamental technologies in modern semiconductor design, including on-chip interconnects, power management units, and physical chip layout techniques critical for performance and reliability.
• Key Procedural History: The complaint alleges Defendant had pre-suit knowledge of four of the five asserted patents. For U.S. Patent Nos. 6,212,633, 7,523,331, and 8,081,026, knowledge is alleged based on their citation during the prosecution of Defendant's own patents. For U.S. Patent No. 7,246,027, knowledge is alleged based on a 2014 notice letter from Plaintiff’s predecessor-in-interest. These allegations form the basis for claims of willful infringement.

Case Timeline

Date	Event
1998-06-26	Priority Date for U.S. Patent No. 6,212,633
2001-04-03	Issue Date for U.S. Patent No. 6,212,633
2003-09-16	Priority Date for U.S. Patent No. 7,523,331
2005-01-11	Priority Date for U.S. Patent No. 7,247,552
2005-03-11	Priority Date for U.S. Patent No. 7,246,027
2007-07-17	Issue Date for U.S. Patent No. 7,246,027
2007-07-24	Issue Date for U.S. Patent No. 7,247,552
2009-04-21	Issue Date for U.S. Patent No. 7,523,331
2010-05-26	Priority Date for U.S. Patent No. 8,081,026
2011-12-20	Issue Date for U.S. Patent No. 8,081,026
2014-05-30	Plaintiff’s predecessor allegedly provided notice to Defendant of the ’027 Patent
2018-06-28	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,212,633 - "Secure data communication over a memory-mapped serial communications interface utilizing a distributed firewall"

The Invention Explained

• Problem Addressed: The patent describes a problem with memory-mapped communication interfaces like IEEE 1394 (FireWire), where data transmissions are broadcast to every device ("node") on the interface without encryption, creating a security vulnerability to interception and unauthorized access (Compl. ¶13; ’633 Patent, col. 2:54-67).
• The Patented Solution: The invention proposes a "distributed firewall" composed of "security managers" located within individual nodes on the interface. These managers are configured to control access to their associated nodes, thereby restricting communications to only authorized entities and enabling secure data transmission without altering the fundamental specifications of the underlying communication protocol (’633 Patent, Abstract; col. 3:52-56).
• Technical Importance: This approach sought to add a layer of security to high-bandwidth, peer-to-peer interfaces that were becoming prevalent for multimedia applications, enabling features like copy protection and confidential data transfer without requiring a completely new interface standard (’633 Patent, col. 3:10-24).

Key Claims at a Glance

• The complaint asserts independent claim 36 (Compl. ¶16).
• Essential elements of Claim 36 include:
  • A method of controlling access between first and second nodes coupled over a memory-mapped serial communications interface supporting peer-to-peer communications.
  • Controlling access to the first node using a first security manager disposed in the first node.
  • Assigning the first node a segment of memory addresses with secure and unsecure portions.
  • Configuring the first security manager to control access only to the secure portion.
  • Controlling access to a second node using a second security manager in the second node.
  • Wherein the first and second security managers define a distributed firewall for the interface.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,246,027 - "Power optimization of a mixed-signal system on an integrated circuit"

The Invention Explained

• Problem Addressed: The patent addresses the need for power optimization in portable electronics, noting that integrated circuits consume more power than necessary because they are designed for worst-case operational assumptions, failing to account for chip-by-chip variations from the manufacturing process (Compl. ¶¶43-44; ’027 Patent, col. 2:8-16).
• The Patented Solution: The invention provides a method for increasing power supply efficiency by determining an "analog variation parameter" that represents the specific fabrication process variance of an individual integrated circuit. This parameter, along with the operational temperature, is used to determine an adjustment signal for the power supply, optimizing power consumption on a per-chip basis rather than for a generic worst-case scenario (’027 Patent, Abstract; col. 2:40-51).
• Technical Importance: This technique allows for more granular, dynamic power management in system-on-a-chip (SoC) devices, improving battery life in portable electronics by tailoring voltage levels to the actual, measured characteristics of each individual chip (’027 Patent, col. 1:7-10).

Key Claims at a Glance

• The complaint asserts independent claim 18 (Compl. ¶47).
• Essential elements of Claim 18 include:
  • A method for increasing power supply efficiency of an integrated circuit.
  • Determining an analog variation parameter representative of an integrated circuit fabrication process variance.
  • Determining an adjustment signal for a power supply voltage level based on the analog variation parameter.
  • Adjusting a regulation signal of a DC-to-DC converter based on the adjustment signal to optimize power consumption.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,247,552 - "Integrated circuit having structural support for a flip-chip interconnect pad and method therefor"

Technology Synopsis

The patent addresses the problem of mechanical stress and dielectric cracking under the bond pads of integrated circuits during the flip-chip packaging process (Compl. ¶67). The solution involves a method of designing the circuit layout by defining a "force region" under the bond pad, identifying interconnect layers within that region that have a metal density below a predetermined percentage, and modifying the layout by adding non-functional "dummy metal lines" to those layers to increase their metal density and provide greater structural support (Compl. ¶¶67, 81-82).

Asserted Claims

Independent claim 11 (Compl. ¶69).

Accused Features

The complaint accuses Intel's method of manufacturing integrated circuits, such as the i7-4770 processor, which allegedly includes adding dummy metal lines to reinforce regions under bond pads (Compl. ¶¶68, 71, 82). An electron micrograph in the complaint purports to show a "force region" and "dummy metal lines" in an accused product (Compl. p. 25).

U.S. Patent No. 7,523,331 - "Power saving operation of an apparatus with a cache memory"

Technology Synopsis

The patent describes a method for reducing power consumption in an apparatus with a processor, main memory, and cache memory (Compl. ¶¶94-95). The solution involves loading a program of instructions needed for a low-power function (e.g., an interrupt handler) into the cache memory, and then deactivating the main memory. The processor can then execute the function using only the cache, which consumes less power, without needing to reactivate the main memory (’331 Patent, col. 1:54-66).

Asserted Claims

Independent claim 7 (Compl. ¶98).

Accused Features

The complaint accuses Intel products that include a Management Engine ("ME") and a CPU with a memory controller (Compl. ¶97). The ME is alleged to remain active in low-power states (e.g., S5 state) when the main memory and CPU are turned off, executing functions from its own cache, thereby practicing the claimed method (Compl. ¶¶109-112). A diagram from Intel documentation shows the hardware architecture of the management engine, including its processor, caches, and memory controllers (Compl. p. 31).

U.S. Patent No. 8,081,026 - "Method for supplying an output supply voltage to a power gated circuit and an integrated circuit"

Technology Synopsis

The patent relates to managing the trade-off between speed and power consumption (leakage) in integrated circuits that use power gating (Compl. ¶126). The invention is a method where a control circuit receives a "mode indicator" (e.g., high-performance vs. low-power) and a "leakage indicator" (reflecting the specific leakage characteristics of the chip). Based on these indicators, the control circuit selects and supplies a control signal to a power gating switch, which in turn provides an optimized output voltage to the power-gated circuit (’026 Patent, Abstract).

Asserted Claims

Independent claim 13 (Compl. ¶129).

Accused Features

The complaint accuses Intel products that supply an output supply voltage to a power-gated circuit (Compl. ¶128). It alleges that Intel's Power Control Unit (PCU) acts as the control circuit, receiving mode indicators (e.g., C6 state) and leakage indicators (derived from temperature) to control power gating switches (Compl. ¶¶135-139).

III. The Accused Instrumentality

Product Identification

The complaint accuses a range of Intel products, identified by the specific technological features they contain. These include: Intel products with Intel On-Chip System Fabric ("IOSF") technology; products with a Power Control Unit ("PCU") that compensates for Inverse Temperature Dependence ("ITD"); processors such as the i7-4770 manufactured with certain methods; products with an infringing Management Engine ("ME"); and products that supply voltage to power-gated circuits (Compl. ¶¶15, 46, 68, 97, 128).

Functionality and Market Context

• The accused features represent core functionalities of modern Intel microprocessors and chipsets. The IOSF is described as the internal communication backbone of the chip (Compl. ¶15). The PCU and ME are central to the chips' power and thermal management, which are critical for performance in devices from servers to laptops (Compl. ¶¶46, 97). The manufacturing methods relate to the physical construction of the chips, essential for yield and reliability (Compl. ¶68). Finally, power gating is a fundamental technique for managing power consumption in active use (Compl. ¶128).
• The complaint alleges these features are present in a wide array of commercially significant Intel products that are foundational to the personal computing and server markets. The marketing slide in the complaint for "Skylake Power Management" highlights the importance of high-granularity power gating for performance and battery life (Compl. p. 40).

IV. Analysis of Infringement Allegations

’633 Patent Infringement Allegations

Claim Element (from Independent Claim 36)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of controlling access to first and second nodes from a plurality of nodes coupled to one another over a memory-mapped serial communications interface of the type supporting peer-to-peer communications between the plurality of nodes...	Intel's accused products use the Intel On-Chip System Fabric (IOSF) Sideband, which is alleged to be a memory-mapped serial interface supporting peer-to-peer communication between agents such as the Intel ME and PMC circuits.	¶¶17-22	col. 2:31-42
a) controlling access to the first node using a first security manager disposed in the first node,	A Policy Enforcer (371), alleged to be a security manager, is located in each IOSF sideband agent (the "first node") and controls access to that agent. A diagram from an Intel patent shows this Policy Enforcer architecture (Compl. p. 7).	¶23	col. 3:52-56
wherein the first node is assigned a segment of memory addresses for the communications interface, the segment of memory addresses including secure and unsecure portions thereof,	The first node is assigned memory-mapped addresses for its registers. For example, setting the Lock_ICCSEC bit makes the address of the ICC Security register a "secure portion," while leaving it unset makes it an "unsecure portion."	¶27	col. 5:58-65
and wherein the first security manager is configured to control access only to the secure portion of the segment of memory addresses for the first node;	Setting the Lock_ICCG1Dyn and/or Lock_ICCSEC bits allegedly triggers the Policy Enforcer to use SAI-based access controls for the corresponding registers, thereby controlling access only to the secure portion of the node's memory addresses.	¶28	col. 6:1-6
(b) controlling access to the second node using a second security manager disposed in the second node	Other sideband nodes (e.g., Intel ME and PMC) also contain their own Policy Enforcer circuits that control access to themselves using SAIs.	¶29	col. 3:10-14
wherein the first and second security managers define a distributed firewall for the communications interface.	The collective action of the individual Policy Enforcers controlling access to their respective nodes is alleged to define a distributed firewall for the IOSF sideband interface.	¶30	col. 3:49-56

Identified Points of Contention

• Scope Questions: A primary question may be whether the term "memory-mapped serial communications interface," which the patent illustrates extensively with the off-chip IEEE 1394 standard, can be construed to read on an internal, proprietary on-chip fabric like Intel's IOSF.
• Technical Questions: The analysis may focus on whether the functionality of Intel's "Policy Enforcer" and "SAI attributes" corresponds to the "security manager" and its method of controlling access as described in the patent, or if there are material operational differences.

’027 Patent Infringement Allegations

Claim Element (from Independent Claim 18)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method for increasing power supply efficiency of an integrated circuit...	The Power Control Unit (PCU) in the accused products is alleged to be designed to maximize power supply efficiency by determining an "optimal voltage at all operating points." A marketing slide illustrates this principle with a voltage-frequency curve (Compl. p. 13).	¶48	col. 2:42-43
determining an analog variation parameter representative of an integrated circuit fabrication process variance of the integrated circuit;	The complaint alleges this is met by the accused products' use of thermal sensors and manufacturing test voltages to compensate for Inverse Temperature Dependence (ITD), an effect tied to the manufacturing process (e.g., 22nm node).	¶49	col. 2:43-46
determining an adjustment signal for a power supply voltage level of the integrated circuit based on the analog variation parameter,	The accused PCU allegedly "interpolates linearly at run time to determine the voltage" based on the thermal sensor information and test voltages, which constitutes the adjustment signal.	¶50	col. 2:48-51
adjusting a regulation signal of a DC-to-DC converter based on the adjustment signal to optimize power consumption of the integrated circuit.	The PCU is alleged to adjust a regulation signal to a voltage regulator (a DC-to-DC converter) via an interface such as the "processor Serial Voltage IDentification (SVID) interface."	¶¶52-53	col. 2:48-51

Identified Points of Contention

• Scope Questions: A central dispute may arise over the definition of "analog variation parameter representative of an integrated circuit fabrication process variance." The question is whether compensating for the ITD effect, which is temperature-dependent, meets this limitation, or if the claim requires a more direct measurement of a parameter tied to manufacturing inconsistencies (e.g., transistor threshold voltage).
• Technical Questions: What evidence does the complaint provide that the accused method is based on "fabrication process variance" as opposed to solely "operational temperature"? The complaint links the ITD effect to the "22nm node," suggesting a connection to the fabrication process (Compl. ¶¶49, p. 14), but the operational description focuses on temperature.

V. Key Claim Terms for Construction

Patent: ’633 Patent

• The Term: "memory-mapped serial communications interface"
• Context and Importance: The applicability of the patent to the accused IOSF technology hinges on this term's construction. Practitioners may focus on whether this term is limited to external bus standards like IEEE 1394, which dominate the patent's specification, or if it can broadly cover proprietary, on-chip interconnects.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself is not explicitly limited to any particular standard (e.g., IEEE 1394) or to an external, off-chip interface (’633 Patent, col. 22:40-45).
  • Evidence for a Narrower Interpretation: The specification's background and detailed description extensively and repeatedly reference the IEEE 1394 specification as the context for the invention, which could support an argument that the claims should be interpreted in light of that context (’633 Patent, col. 2:10-51; col. 5:10-15).

Patent: ’027 Patent

• The Term: "analog variation parameter representative of an integrated circuit fabrication process variance"
• Context and Importance: This term is the technological core of the asserted claim. The infringement case depends on whether Intel's method of compensating for Inverse Temperature Dependence (ITD) by using thermal sensors and interpolating test voltages qualifies as "determining" such a parameter.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself is broad. Any analog parameter that changes as a result of manufacturing variations could potentially fall within its scope. The abstract describes the invention as "determining an analog variation parameter that is representative of an integrated circuit fabrication process variance," without further limitation (’027 Patent, Abstract).
  • Evidence for a Narrower Interpretation: The specification distinguishes between the "analog variation parameter" and "operational temperature," treating them as two separate inputs for determining the final adjustment signal (’027 Patent, Abstract). This could support an argument that a parameter based solely on temperature (as the complaint alleges for ITD compensation) is not the claimed "analog variation parameter."

VI. Other Allegations

• Indirect Infringement: For all five asserted patents, the complaint alleges induced infringement, stating that Defendant provides documentation, datasheets, and developer's manuals that instruct customers on how to use the accused products in an infringing manner (e.g., Compl. ¶¶32, 55, 114). It also alleges contributory infringement on the basis that the accused products are a material part of the patented inventions and are not staple articles of commerce suitable for substantial non-infringing use (e.g., Compl. ¶¶33, 56, 115).
• Willful Infringement: The complaint alleges willful infringement for all five patents. It asserts that Defendant had pre-suit knowledge of the ’633, ’331, and ’026 Patents because they were cited during the prosecution of Intel's own patents (Compl. ¶¶31, 113, 142). For the ’027 Patent, knowledge is alleged based on a May 30, 2014 notice letter from Plaintiff's predecessor, Freescale (Compl. ¶54). For the ’552 Patent, knowledge is alleged as of at least the filing of the complaint (Compl. ¶84). The complaint further alleges that Defendant was willfully blind to the existence of the patents due to a "publicly-known corporate policy forbidding its employees from reading patents held by outside companies" (Compl. ¶31).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can claim terms rooted in the context of older, off-chip communication standards (e.g., "memory-mapped serial communications interface" in the '633 Patent, which heavily cites IEEE 1394) be construed to cover modern, proprietary, integrated on-chip fabrics?
• A key question of technical interpretation will be central to the power management patents: does compensating for a temperature-dependent physical effect (Inverse Temperature Dependence) constitute the determination of an "analog variation parameter representative of... fabrication process variance" as required by the ’027 Patent, or is there a fundamental mismatch in the technical basis of the accused method?
• The case may also turn on a question of functional proof: while the complaint cites extensive public documentation, a critical issue will be whether discovery confirms that the internal operations of complex features like the Power Control Unit and Management Engine function precisely as required by the specific, multi-step limitations of the asserted method claims.