DCT
1:18-cv-01065
Altair Logix LLC v. Texas Instruments Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: Texas Instruments Incorporated (Delaware)
- Plaintiff’s Counsel: STAMOULIS & WEINBLATT LLC
- Case Identification: Altair Logix LLC v. Texas Instruments Incorporated, 1:18-cv-01065, D. Del., 07/18/2018
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because the Defendant is a Delaware corporation.
- Core Dispute: Plaintiff alleges that Defendant’s multicore System-on-Chip products infringe a patent related to dynamically reconfigurable circuits for media processing.
- Technical Context: The technology concerns dynamically reconfigurable processor architectures designed to provide the high performance of fixed-function hardware with the flexibility of programmable systems, a central challenge in modern System-on-Chip (SoC) design.
- Key Procedural History: The complaint alleges that Claim 1 of the asserted patent was an originally filed claim that issued without amendment and without any anticipation rejection during prosecution, a point Plaintiff may use to argue for the claim's novelty and broad scope.
Case Timeline
| Date | Event |
|---|---|
| 1997-02-28 | U.S. Patent No. 6,289,434 Priority Date |
| 2001-09-11 | U.S. Patent No. 6,289,434 Issues |
| 2018-07-18 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"
- Patent Identification: U.S. Patent No. 6,289,434 (“the ’434 Patent”), titled “Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates,” issued on September 11, 2001.
The Invention Explained
- Problem Addressed: The patent’s background section describes a trade-off in integrated circuit design between high-performance, cost-inefficient "fixed-function" hardware and more flexible but lower-performance programmable devices like Digital Signal Processors (DSPs) and Field-Programmable Gate Arrays (FPGAs) (Compl. ¶¶13-17; ’434 Patent, col. 1:42-2:39). Fixed-function systems suffer from "temporal redundancy," meaning they must implement all possible functions on silicon, even those not in use at a given moment, increasing cost and chip area (’434 Patent, col. 2:50-60; Compl. ¶19).
- The Patented Solution: The invention proposes an apparatus of interconnected "media processing units" that can be dynamically and adaptively reconfigured at run-time. This solution aims to reduce cost by "removing redundancy" through the re-use of computational and storage elements in different configurations as needed (’434 Patent, col. 3:1-11; Compl. ¶20). The architecture, depicted in Figure 3 of the patent, uses a memory-mapped protocol to manage the reconfiguration and data flow between these processing units (’434 Patent, col. 4:26-38).
- Technical Importance: This architectural approach sought to bridge the gap between application-specific integrated circuits (ASICs) and general-purpose processors, a critical area of innovation for creating powerful and efficient SoCs for media-intensive applications (Compl. ¶12).
Key Claims at a Glance
- The complaint asserts independent Claim 1 (’434 Patent, col. 55:20-56:33; Compl. ¶26).
- The essential elements of Claim 1 include:
- An apparatus with an addressable memory for storing data and instructions.
- A plurality of "media processing units," each coupled to the memory.
- Each media processing unit comprising a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit (BMU).
- The ALU must be capable of operating concurrently with the multiplier and/or the arithmetic unit.
- The BMU must be capable of operating concurrently with the ALU and at least one of the multiplier or the arithmetic unit.
- Each media processing unit must be capable of performing an operation simultaneously with other media processing units.
- An "operation" is defined as receiving an instruction and data from memory, processing the data, and providing a result.
- The prayer for relief seeks judgment on "one or more claims," but the infringement allegations in the complaint focus exclusively on Claim 1 (Compl. ¶¶26, 36; Prayer for Relief ¶a).
III. The Accused Instrumentality
Product Identification
- The Texas Instruments 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (“Accused Instrumentality”) (Compl. ¶26).
Functionality and Market Context
- The Accused Instrumentality is a System-on-Chip that integrates multiple processor cores, including a "Quad Core ARM CorePac" containing four ARM Cortex-A15 processors and eight C66x DSP cores (Compl. ¶¶27, 28, 33).
- The complaint alleges that the ARM Cortex-A15 processors, each incorporating a NEON media coprocessor, function as the claimed "media processing units" (Compl. ¶28). These processors are coupled to a shared memory system that includes on-chip SRAM and an interface for external DDR3 memory (Compl. ¶27). The complaint references a block diagram from the product datasheet to illustrate this architecture (Compl. ¶28, p. 12). This diagram shows the four ARM A15 cores and their relationship to the shared memory controller.
IV. Analysis of Infringement Allegations
'434 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an addressable memory for storing the data, and a plurality of instructions... | The memory subsystem of the Accused Instrumentality, including the 6MB of Multicore Shared Memory (MSM) SRAM and DDR3 EMIF (Compl. p. 10). | ¶27 | col. 55:21-28 |
| a plurality of media processing units... | The four ARM® Cortex®-A15 MPCore™ Processors within the ARM CorePac, which operate simultaneously (Compl. p. 12). | ¶28 | col. 55:29-31 |
| a multiplier having a data input... | The Integer MUL or FP MUL unit within the NEON media coprocessor of each ARM Cortex-A15 processor, as shown in a NEON pipeline diagram (Compl. p. 14). | ¶29 | col. 55:31-35 |
| an arithmetic unit having a data input... | The FP ADD unit within the NEON media coprocessor of each ARM Cortex-A15 processor. | ¶30 | col. 55:36-40 |
| an arithmetic logic unit... capable of operating concurrently with at least one selected from the multiplier and arithmetic unit... | The Integer ALU within the NEON media coprocessor, which is alleged to be capable of operating concurrently with the Integer MUL/FP MUL and FP ADD units. | ¶31 | col. 55:41-47 |
| a bit manipulation unit... capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit... | The Integer Shift unit within the NEON media coprocessor, which is alleged to be capable of operating concurrently with the other specified units. | ¶32 | col. 55:48-56 |
| each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units... | The simultaneous operation of the multiple ARM Cortex-A15 multicore processors on the same chip. | ¶33 | col. 56:21-24 |
| each operation comprising: receiving... instruction... data... processing the data... and providing... a result... | Each ARM Cortex-A15 processor allegedly receives instructions and data from the memory system, processes it, and produces a result to be provided at its input/output. | ¶¶34-35 | col. 56:25-33 |
- Identified Points of Contention:
- Scope Questions: A primary dispute may arise over the definition of "media processing unit." The patent describes this unit as part of an architecture for "adaptively dynamically reconfiguring groups of computational and storage elements" to reduce redundancy (’434 Patent, col. 3:14-18). The question for the court will be whether the accused architecture of standard ARM cores with NEON SIMD (Single Instruction, Multiple Data) coprocessors meets this specific definition of a dynamically reconfigurable unit, or if it represents a different, conventional approach to parallel processing.
- Technical Questions: The claim requires specific concurrency capabilities between the multiplier, arithmetic unit, ALU, and bit manipulation unit. The complaint alleges this concurrency is met by the pipelined architecture of the NEON coprocessor (Compl. ¶¶31-32). A potential point of contention is whether the pipelined execution in the Accused Instrumentality constitutes the "concurrent" operation required by the claim, particularly in light of the patent's disclosure of executing "three concurrent 32 bit arithmetic or logical operations in parallel" in a single clock cycle (’434 Patent, col. 4:40-44).
V. Key Claim Terms for Construction
The Term: "media processing unit"
- Context and Importance: This term is the fundamental building block of the claimed apparatus. The outcome of the infringement analysis depends heavily on whether the accused ARM Cortex-A15 processors with NEON coprocessors fall within the scope of this term.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent abstract refers to the elements as "processors" that can perform various functions, and the specification frequently uses the term "MPU" ('434 Patent, col. 4:30), which could support mapping the term to the accused ARM processors.
- Evidence for a Narrower Interpretation: The patent repeatedly frames the invention as a "new apparatus" that achieves lower cost by "removing redundancy" via "re-using groups of computational and storage elements in different configurations" (’434 Patent, col. 2:64-3:4). A party may argue this language limits a "media processing unit" to an element within such a specific reconfigurable architecture, distinguishing it from a conventional multicore processor.
The Term: "capable of operating concurrently"
- Context and Importance: This limitation defines the required operational relationship between the functional sub-units (ALU, BMU, etc.) within each "media processing unit." Infringement requires showing that the accused NEON coprocessor has this specific capability.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue that "concurrently" is satisfied by a modern pipelined architecture where different functional units are active in the same clock cycle, albeit on different instructions. The complaint's reliance on pipeline diagrams suggests this interpretation (Compl. p. 14).
- Evidence for a Narrower Interpretation: The specification states that the invention may "execute three concurrent 32 bit arithmetic or logical operations in parallel while accessing four 32 bit data words from memory... all this in a single clock cycle" (’434 Patent, col. 4:40-44). A party could seize on the term "in parallel" to argue for a requirement of true simultaneous execution of multiple independent operations, potentially beyond standard pipelining.
VI. Other Allegations
No indirect or willful infringement is alleged in the complaint.
VII. Analyst’s Conclusion: Key Questions for the Case
The resolution of this dispute will likely depend on the court's determination of two central questions:
- A core issue will be one of architectural definition: Can the term "media processing unit," which is rooted in the patent's specific teachings of a dynamically reconfigurable architecture for reducing hardware redundancy, be construed to read on the accused product's architecture of conventional ARM processor cores paired with a NEON SIMD coprocessor?
- A key evidentiary question will be one of functional concurrency: Does the accused NEON coprocessor's pipelined execution model satisfy Claim 1's requirement that certain functional units are "capable of operating concurrently," or will the patent's disclosure of executing multiple operations "in parallel" in a "single clock cycle" be interpreted to require a higher degree of simultaneous operation than the accused device provides?