DCT

1:18-cv-01729

Super Interconnect Tech LLC v. Lenovo Holding Co Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:18-cv-01729, D. Del., 11/02/2018
  • Venue Allegations: Venue is alleged to be proper for Lenovo Group Ltd. as a foreign entity that may be sued in any judicial district. For the domestic Lenovo entities, venue is alleged to be proper because they are incorporated under the laws of Delaware and therefore reside in the District.
  • Core Dispute: Plaintiff alleges that Defendant’s Lenovo Miix 630 tablet, which incorporates Universal Flash Storage (UFS), infringes patents related to high-speed serial data transmission and clocking.
  • Technical Context: The technology at issue concerns methods for transmitting clock, data, and control signals over a single, low-power serial communication link, a critical technology for connecting components like processors and storage in modern mobile devices.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
1998-09-10 Priority Date for U.S. Patent No. 6,463,092
2001-03-16 Priority Date for U.S. Patent No. 7,158,593
2002-10-08 Issue Date for U.S. Patent No. 6,463,092
2005-10-31 Priority Date for U.S. Patent No. 7,627,044
2007-01-02 Issue Date for U.S. Patent No. 7,158,593
2009-12-01 Issue Date for U.S. Patent No. 7,627,044
2018-11-02 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,627,044 - “Clock-Edge Modulated Serial Link with DC-Balance Control,” Issued December 1, 2009

The Invention Explained

  • Problem Addressed: The patent describes the need for a low-power serial link for mobile devices to reduce the power consumption, physical space, and electromagnetic radiation associated with conventional multi-line parallel interfaces (’044 Patent, col. 1:11-40). Existing serial links often require a separate clock channel or a local reference clock at the receiver, which increases hardware costs and complexity (’044 Patent, col. 1:41-54).
  • The Patented Solution: The invention proposes a single-channel serial link that transmits clock, data, and control signals simultaneously. It uses clock-edge modulation (CEM), where data is encoded by varying the position of a clock pulse’s edge (e.g., the falling edge) while keeping the other edge periodic for clock recovery (’044 Patent, Abstract). The key aspect is the incorporation of direct current (DC) balancing control signals directly into the pulse-width modulated signal to maintain signal integrity over the channel, for instance by coding a "1" bit as either a 25% or 75% duty cycle pulse depending on the running DC value (’044 Patent, col. 3:19-41).
  • Technical Importance: This design allows for a single, low-power, high-speed interface that does not require a separate clock line, making it particularly suitable for compact, battery-powered devices where power and cost are primary constraints (’044 Patent, col. 2:19-24).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶16).
  • Essential elements of claim 1, a signal transmitter, include:
    • A channel node to interface with a single direct current balanced differential channel.
    • Circuitry connected to the channel node.
    • The circuitry configured to multiplex clock, data and control signals and apply them to the channel node.
    • Wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.
  • The complaint reserves the right to assert other claims, including dependent claims 2, 8-15, and 19 (Compl. ¶15).

U.S. Patent No. 6,463,092 - “System and Method for Sending and Receiving Data Signals Over A Clock Signal Line,” Issued October 8, 2002

The Invention Explained

  • Problem Addressed: The patent identifies two issues with prior art data communication systems. First, dedicating channel bandwidth to control signals reduces the bandwidth available for primary data, and second, many systems lack a mechanism for the receiver to send signals back to the transmitter without adding separate, costly physical lines (’092 Patent, col. 1:46-56, col. 2:5-16).
  • The Patented Solution: The invention discloses a system where a single transmission line is used to send both a clock signal and a data signal from a transmitter to a receiver. This is accomplished by modulating data onto the clock signal, such as by varying the position of the falling edge while preserving the rising edge for clock recovery (’092 Patent, col. 4:27-36). The system also uniquely enables bi-directional communication by allowing the receiver to superimpose a return data signal onto the same transmission line, which the transmitter then filters and decodes using a specialized line interface (’092 Patent, Abstract; col. 4:63-col. 5:14).
  • Technical Importance: This innovation enabled the creation of a bi-directional communication link over a single channel that would traditionally have been unidirectional, thereby reducing pin count and system complexity while providing a return path for control signals or other data (’092 Patent, col. 2:1-4).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶31).
  • Essential elements of claim 1, an apparatus for transmitting, include:
    • A clock generator with a first input, a second input, and an output.
    • The clock generator modulating a falling edge of an output signal to indicate different data values.
    • The first input of the clock generator coupled to receive a clock signal.
    • The second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted.
  • The complaint reserves the right to assert other claims, including dependent claims 2, 5, 10, and 11 (Compl. ¶30).

Multi-Patent Capsule: U.S. Patent No. 7,158,593 - “Combining a Clock Signal and a Data Signal,” Issued January 2, 2007

  • Technology Synopsis: This patent focuses on improving the reliability of transmitting a combined clock and data signal over a single channel (’593 Patent, col. 1:32-46). The solution involves applying a specific encoding scheme to the data before it is modulated onto the clock signal. This encoding shifts the data signal's energy spectrum to higher frequencies, moving it away from the effective loop bandwidth of the clock recovery circuit (e.g., a Phase-Locked Loop) at the receiver. This separation reduces jitter and interference, enabling more robust data recovery, particularly at high transmission speeds (’593 Patent, Abstract; col. 2:56-65).
  • Asserted Claims: The complaint asserts independent claim 34 (Compl. ¶46).
  • Accused Features: The complaint alleges that the UFS devices in the accused product contain transmitters that use an encoding scheme to shift the energy spectrum of the combined signal away from the clock recovery block's bandwidth before multiplexing the signals onto the communications channel (Compl. ¶50).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the Lenovo Miix 630 tablet as the exemplary accused product (Compl. ¶15, ¶30, ¶45).

Functionality and Market Context

  • The complaint alleges that the Lenovo Miix 630 tablet incorporates Universal Flash Storage (UFS) 2.1 (Compl. ¶18). A screenshot of the product's technical specifications is provided as evidence for this feature (Compl. ¶18). The complaint further alleges that this UFS implementation utilizes the MIPI M-PHY protocol for its physical communication layer, which is responsible for the actual signaling between the UFS host and the UFS device (Compl. ¶19). A block diagram from a technical white paper is included to illustrate this UFS host-to-device interface via the M-PHY layer (Compl. ¶19, Figure 2). The core infringement theory is that the signal transmitters within this UFS/M-PHY system perform the patented methods of combining, modulating, and transmitting clock and data signals (Compl. ¶20, ¶35, ¶50).

IV. Analysis of Infringement Allegations

'044 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a channel node to interface with a single direct current balanced differential channel The UFS hosts and devices in the accused product contain signal transmitters that drive a DC-balanced differential signal over a communications channel. ¶20 col. 2:5-7
circuitry connected to the channel node, The signal transmitters within the UFS hosts and devices constitute the claimed circuitry. ¶20 col. 2:8-12
the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node, The accused transmitters allegedly "multiplex a pulse-width modulated clock signal, a data signal, and control signals to apply them to the communications channel." ¶20 col. 2:8-12
wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals. The complaint alleges that the accused transmitters generate signals that are pulse-width modulated and that this modulation is used to incorporate DC-balancing, pointing to the M-PHY protocol used by the UFS storage. ¶20 col. 2:10-12
  • Identified Points of Contention:
    • Scope Questions: A central question is whether the "DC-balanced differential signal" alleged to be used by the accused UFS standard (Compl. ¶20) is equivalent to a signal that incorporates "direct current balancing control signals" as required by the claim. The claim language suggests the incorporation of discrete control signals, and the court may need to decide if the general DC-balancing codes used in a standard like M-PHY satisfy this more specific limitation.

'092 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a clock generator having a first input, a second input and an output, The UFS hosts and devices in the accused products allegedly "multiplex clock and data signals for transmission over a single communications channel," with this multiplexing functionality serving as the clock generator. ¶35 col. 4:25-28
the clock generator modulating a falling edge of an output signal to indicate different data values, The complaint alleges the clock signal is "modulated based on the data to be transmitted" and points to the M-PHY protocol's use of PWM (Pulse-Width Modulation) signaling, which is a form of clock-edge modulation. ¶35 col. 4:29-32
the first input of the clock generator coupled to receive a clock signal, The accused UFS system uses a reference clock, as shown in the provided block diagram, which serves as the clock signal input. ¶34 col. 4:43-46
the second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted. The data to be transmitted is alleged to be the control signal that dictates the modulation of the clock signal before it is combined with the output data stream. ¶35 col. 4:47-52
  • Identified Points of Contention:
    • Technical Questions: The claim requires "modulating a falling edge." The complaint alleges the accused product uses PWM signaling (Compl. ¶34, ¶35). While PWM inherently alters the position of one edge relative to the other, the key question for the court will be an evidentiary one: does the specific M-PHY implementation in the accused product operate by modulating the falling edge, as explicitly recited in the claim, or does it modulate the rising edge or both?

V. Key Claim Terms for Construction

For the ’044 Patent:

  • The Term: "direct current balancing control signals"
  • Context and Importance: This term is central to the infringement analysis for the '044 patent. The dispute will likely focus on whether the method of DC-balancing employed by the accused UFS/M-PHY standard falls within the scope of this term. Practitioners may focus on this term because the complaint's evidence points to a "DC-balanced signal" generally, while the claim requires the incorporation of specific "control signals."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification discusses the invention in terms of a "signal transmitter... configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals" (’044 Patent, col. 2:1-5), which a party could argue supports a functional definition covering any signal that achieves DC balance via modulation.
    • Evidence for a Narrower Interpretation: The patent provides a specific embodiment where the bit "1" is coded as either a 25% duty cycle ("1-") or a 75% duty cycle ("1+") pulse, with the choice being a "control signal" determined by the running DC value of previously transmitted bits (’044 Patent, col. 3:31-41). A party could argue the term should be limited to this explicit scheme of distinct control states.

For the ’092 Patent:

  • The Term: "modulating a falling edge"
  • Context and Importance: Infringement of claim 1 of the '092 patent hinges on this limitation. The analysis will require determining if the accused product's alleged PWM signaling constitutes a modulation of the "falling edge."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The abstract describes a clock generator that "produces a clock signal that includes a variable position falling edge" (’092 Patent, Abstract). A party might argue that any modulation technique (like PWM) that results in a variable falling edge position satisfies this language, regardless of the precise mechanism.
    • Evidence for a Narrower Interpretation: The detailed description repeatedly emphasizes that the "activity for a bi-directional data link... is centered around the falling edge of the clock" and that this "preserves the rising edge of the clock for clock recovery" (’092 Patent, col. 4:33-36). A party could argue this requires an intentional and direct manipulation of the falling edge timing itself, not merely an emergent property of varying a pulse's overall width.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Lenovo actively induces infringement by third parties (e.g., consumers) by, among other things, creating advertisements, establishing distribution channels for the accused products, and making available instructions and user manuals that promote the infringing use (Compl. ¶24, ¶39, ¶54).
  • Willful Infringement: The complaint alleges that Lenovo has known of its infringement "at least as early as the service date of this Original Complaint" (Compl. ¶23, ¶38, ¶53). This allegation supports a claim for post-suit willful infringement but does not allege any pre-suit knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

This case appears to center on the intersection of broad patent claims and the specific technical operations of an industry standard. The outcome will likely depend on the court’s resolution of two primary issues:

  • A core issue will be one of technical and evidentiary mapping: Can the plaintiff prove that the high-level descriptions of the UFS and MIPI M-PHY standards, as implemented in the Lenovo Miix 630, perform the specific functions recited in the claims? For instance, does the accused product's general "DC-balancing" functionality operate by incorporating the discrete "direct current balancing control signals" required by the '044 patent, and does its PWM signaling constitute the specific "modulating a falling edge" required by the '092 patent?
  • A related and dispositive issue will be one of claim construction: How narrowly will the court define the key terms of the asserted claims? The case may turn on whether terms like "direct current balancing control signals" are given a broad, functional meaning or are construed more narrowly to cover only the specific embodiments disclosed in the patent specifications.