Super Interconnect Tech LLC v. Motorola Mobility LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Super Interconnect Technologies LLC (Texas)
  • Defendant: Motorola Mobility LLC (Delaware)
  • Plaintiff’s Counsel: Farnan LLP
• Case Identification: 1:18-cv-01730, D. Del., 11/02/2018
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because Motorola Mobility LLC was formed under the laws of Delaware and therefore resides in the District.
• Core Dispute: Plaintiff alleges that Defendant’s Motorola Moto Z series smartphones, which incorporate Universal Flash Storage (UFS), infringe three patents related to methods for transmitting clock, data, and control signals over a single serial communication link.
• Technical Context: The technology concerns high-speed, low-power serial interconnects used for component-level communication, such as between a processor and flash memory, within modern mobile devices.
• Key Procedural History: The complaint does not allege any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
1998-09-10	’092 Patent Priority Date
2001-03-16	’593 Patent Priority Date
2002-10-08	’092 Patent Issue Date
2005-10-31	’044 Patent Priority Date
2007-01-02	’593 Patent Issue Date
2009-12-01	’044 Patent Issue Date
2018-11-02	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,627,044 - “Clock-Edge Modulated Serial Link with DC-Balance Control,” issued December 1, 2009

The Invention Explained

• Problem Addressed: The patent describes the challenge in mobile devices of reducing power consumption and hardware costs associated with communication interfaces. Prior art serial links often required a separate, dedicated channel for clock transmission in addition to data channels, which increases pin count and power usage. (’044 Patent, col. 1:46-58).
• The Patented Solution: The invention proposes a single-channel serial link that transmits clock, data, and control signals together. It uses clock-edge modulation (CEM), a form of pulse-width modulation (PWM), to encode information. Crucially, the system incorporates direct current (DC) balancing control signals into the modulated clock signal to maintain signal integrity over the single channel. (’044 Patent, Abstract; col. 2:5-13).
• Technical Importance: This approach allows for a significant reduction in the physical interface complexity and power draw in battery-powered devices by combining multiple signal types onto a single, DC-balanced differential channel. (’044 Patent, col. 1:53-58).

Key Claims at a Glance

• The complaint asserts independent claim 1.
• Essential elements of claim 1 (a signal transmitter) include:
  • A channel node for interfacing with a single direct current balanced differential channel.
  • Circuitry connected to the node configured to multiplex clock, data, and control signals and apply them to the channel node.
  • The clock signal is pulse-width modulated to incorporate direct current balancing control signals.
• The complaint reserves the right to assert dependent claims 2, 8, 9, 10, 11, 12, 13, 14, 15, and 19 (Compl. ¶12).

U.S. Patent No. 6,463,092 - “System and Method for Sending and Receiving Data Signals Over A Clock Signal Line,” issued October 8, 2002

The Invention Explained

• Problem Addressed: The patent identifies limitations in prior art communication systems that require separate physical lines for clock and data signals, reducing available bandwidth and introducing latency for control signals. A further problem noted is the lack of an efficient mechanism for a receiver to send data back to the transmitter. (’092 Patent, col. 2:5-19).
• The Patented Solution: The invention discloses a communication system where a transmitter embeds data onto a clock signal by modulating the position of the clock signal’s falling edge, while the rising edge remains periodic for clock recovery. The receiver decodes the data by observing the falling edge's position. The patent also describes a method for bi-directional communication, where the receiver can superimpose its own return signal onto the same line. (’092 Patent, Abstract; col. 4:27-39).
• Technical Importance: This design enables both forward data transmission and a return data channel over a single clock line, which can reduce system complexity, hardware costs, and latency in communications between components. (’092 Patent, col. 2:1-4).

Key Claims at a Glance

• The complaint asserts independent claim 1.
• Essential elements of claim 1 (an apparatus for transmitting) include:
  • A clock generator with a first input, a second input, and an output.
  • The clock generator modulates a falling edge of an output clock signal to indicate different data values.
  • The first input is coupled to receive a clock signal.
  • The second input is coupled to receive a control signal indicating the data value to be transmitted.
• The complaint reserves the right to assert dependent claims 2, 5, 10, and 11 (Compl. ¶27).

Multi-Patent Capsule: U.S. Patent No. 7,158,593

• Patent Identification: U.S. Patent No. 7,158,593, “Combining a Clock Signal and a Data Signal,” issued January 2, 2007 (Compl. ¶39).
• Technology Synopsis: This patent addresses the problem of jitter and signal degradation when combining data and clock signals on a single channel. The proposed solution is to first use an encoding scheme on the data signal that shifts its energy spectrum away from the energy spectrum of the clock signal. The encoded data is then modulated onto the clock signal, allowing a receiver's clock recovery circuit (e.g., a phase-locked loop) to more easily filter out the data-related noise and recover a clean clock. (’593 Patent, Abstract; col. 1:50-66).
• Asserted Claims: The complaint asserts independent claim 34 and dependent claim 35 (Compl. ¶¶42-43).
• Accused Features: The complaint alleges that the UFS systems in the accused smartphones employ an encoding scheme that shifts the energy spectrum of the data signal before multiplexing it with a clock signal for transmission over a single channel (Compl. ¶47).

III. The Accused Instrumentality

Product Identification

The Motorola Moto Z and Motorola Moto Z Force smartphones (Compl. ¶12).

Functionality and Market Context

• The complaint alleges that these smartphones incorporate Universal Flash Storage (UFS) for their internal storage (Compl. ¶15). The complaint provides a screenshot of the product specifications for the Moto Z, highlighting "64GB UFS" storage (Compl. ¶15).
• The core of the infringement allegation centers on the physical communication layer of the UFS implementation. The complaint alleges this layer uses the MIPI M-PHY protocol, which involves UFS hosts and devices containing signal transmitters (Compl. ¶¶16-17). These transmitters are alleged to multiplex or combine clock, data, and control signals for transmission over a single, DC-balanced differential communications channel (Compl. ¶¶17, 32, 47).
• To support its technical allegations, the complaint includes a block diagram from an Arasan Chip Systems white paper titled "UFS Implementation Detail," which illustrates the interface between a UFS host and a UFS device (Compl. ¶¶16, 31, 46).

IV. Analysis of Infringement Allegations

7,627,044 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A signal transmitter, comprising: a channel node to interface with a single direct current balanced differential channel; and circuitry...configured to multiplex clock, data and control signals and apply them to the channel node,	The UFS hosts and devices in the accused products allegedly contain signal transmitters that drive a DC-balanced differential signal for a communications channel. These transmitters are alleged to multiplex a clock signal, a data signal, and control signals onto the communications channel.	¶17	col. 2:7-11
wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.	The transmitters allegedly multiplex a "pulse-width modulated clock signal" and drive a "DC-balanced differential signal." The complaint alleges this functionality infringes the claim.	¶17	col. 2:10-13

Identified Points of Contention (’044 Patent)

• Technical Question: The complaint alleges the accused product uses a "pulse-width modulated clock signal" and produces a "DC-balanced differential signal." A key question is whether the DC balancing is achieved by the pulse-width modulation of the clock, as required by the claim, or through an independent mechanism, such as a line code (e.g., 8b/10b encoding) applied to the data before modulation.
• Scope Question: Does the term "direct current balancing control signals" read on the inherent DC-balancing properties of a standardized line code, or does it require discrete, dedicated control signals that are actively incorporated into the clock signal, as shown in the patent's embodiments?

6,463,092 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An apparatus for transmitting a clock signal and data signals over a signal line, the apparatus comprising a clock generator having a first input, a second input and an output,	The accused UFS hosts and devices are alleged to "multiplex clock and data signals for transmission over a single communications channel," which implies the presence of an apparatus or generator.	¶32	col. 4:25-27
the clock generator modulating a falling edge of an output clock signal to indicate different data values,	The complaint alleges that in the accused products, the "clock signal is modulated based on the data to be transmitted before being combined with the output data stream."	¶32	col. 4:29-32
the first input of the clock generator coupled to receive a clock signal, and	The alleged multiplexing of clock and data signals implies an input clock signal is provided to the generating circuitry.	¶32	col. 4:43-46
the second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted.	The alleged multiplexing of clock and data signals implies an input data signal is provided to the generating circuitry.	¶32	col. 4:46-48

Identified Points of Contention (’092 Patent)

• Technical Question: Does the modulation scheme used in the accused MIPI M-PHY standard specifically map to "modulating a falling edge" of the clock? The defense may argue that the standard employs a different technique for combining clock and data that does not isolate modulation to a single edge while preserving the other for clock recovery.
• Evidentiary Question: The complaint's allegations are based on high-level descriptions of UFS and MIPI M-PHY. A central issue will be what discovery reveals about the actual, specific operation of the circuitry inside Motorola's devices.

V. Key Claim Terms for Construction

For the ’044 Patent

• The Term: "direct current balancing control signals"
• Context and Importance: This term is central to the patent's novelty, which is the incorporation of DC balancing into a single-channel CEM link. Infringement will depend on whether the method of DC balancing in the accused UFS system falls within the scope of this term. Practitioners may focus on this term because common standards like MIPI M-PHY often achieve DC balance through line coding (e.g., 8b/10b) rather than explicit "control signals" added to a clock.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim uses the functional phrase "to incorporate," which a plaintiff might argue covers any mechanism that results in DC balancing being part of the final modulated signal. The specification describes the purpose as being to "maintain DC-balance, increase DC-balance, and decrease DC-balance" (’044 Patent, col. 3:22-24), which could support a broad, effects-based definition.
  • Evidence for a Narrower Interpretation: The specific embodiment describes encoding the bit "1" as either "1-" (25% duty cycle) or "1+" (75% duty cycle) based on the running DC value (’044 Patent, col. 3:29-39, Fig. 2A). A defendant could argue this ties the term to a specific, active control choice for each transmitted bit, rather than an inherent, passive property of a data-encoding scheme.

For the ’092 Patent

• The Term: "modulating a falling edge"
• Context and Importance: The infringement theory for claim 1 depends entirely on this mechanism. The dispute will likely center on whether the signal combination technique in the accused products is equivalent to the patent's specific method of varying the falling edge's timing while preserving the rising edge.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A plaintiff might argue that any form of pulse-width modulation where data is encoded in the pulse duration necessarily involves "modulating a falling edge" relative to a rising edge, making the term broadly applicable to PWM-style signaling.
  • Evidence for a Narrower Interpretation: The specification repeatedly highlights the benefit of this specific approach: "This is particularly advantageous because it preserves the rising edge of the clock for clock recovery." (’092 Patent, col. 4:33-35). A defendant could use this language to argue that the term requires the rising edge to be substantially fixed and periodic, and that any system that modulates both edges or uses a different clock recovery scheme would not infringe.

VI. Other Allegations

Indirect Infringement

For all three patents-in-suit, the complaint alleges induced infringement under 35 U.S.C. § 271(b). The allegations are based on Motorola's knowledge of the patents (at least from the date of the complaint) and affirmative acts intended to cause infringement by third parties, such as creating advertisements, establishing distribution channels, and providing instructions or manuals for the accused smartphones (Compl. ¶¶21, 36, 51).

Willful Infringement

Willfulness is alleged based on Motorola's knowledge of its infringement, which the complaint pleads began "at least as early as the service date of this Original Complaint" (Compl. ¶¶20, 35, 50). This frames the claim around post-suit conduct. The complaint also alleges Motorola acted with "willful blindness of the fact, that the induced acts constitute infringement" (Compl. ¶¶21, 36, 51).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of technical specificity: Do the accused UFS systems, operating under the MIPI M-PHY standard, actually implement the specific modulation and encoding schemes required by the asserted claims? For example, does the system literally "modulat[e] a falling edge" (’092 Patent) and use pulse-width modulation to "incorporate direct current balancing control signals" (’044 Patent), or does it achieve similar results through different, non-infringing technical means?
• A second central question will be evidentiary sufficiency: The complaint's infringement allegations are substantially based on high-level technical documents and standards. The case will likely turn on whether discovery of Motorola's specific, circuit-level implementation confirms these high-level allegations or reveals a dispositive mismatch between the accused technology and the patent claims.
• A third question concerns claim construction and scope: Can the term "direct current balancing control signals" (’044 Patent) be interpreted broadly to encompass the effects of a standard line code (like 8b/10b), or is its meaning restricted to the explicit, discrete control mechanisms described in the patent's preferred embodiments? The outcome of this construction could be determinative for the infringement analysis of the ’044 patent.