Super Interconnect Tech LLC v. Sony Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Super Interconnect Technologies LLC (Texas)
  • Defendant: Sony Corporation (Japan), Sony Mobile Communications AB (Sweden), Sony Mobile Communications (USA) Inc. (Delaware)
  • Plaintiff’s Counsel: Farnan LLP
• Case Identification: 1:18-cv-01731, D. Del., 11/02/2018
• Venue Allegations: Venue is alleged to be proper for Sony Corporation and Sony Mobile Communications AB as foreign entities, and for Sony Mobile Communications (USA) Inc. as a Delaware corporation that resides in the district.
• Core Dispute: Plaintiff alleges that Defendant’s Sony Xperia XZ smartphone, which utilizes Universal Flash Storage (UFS), infringes three patents related to high-speed serial data communication techniques that combine clock, data, and control signals onto a single channel.
• Technical Context: The technology concerns methods for high-speed, low-power data transmission within mobile devices, a critical element for optimizing performance and battery life in the competitive smartphone market.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
1998-09-10	’092 Patent Priority Date
1999-09-09	’593 Patent Priority Date
2002-10-08	’092 Patent Issue Date
2005-10-31	’044 Patent Priority Date
2007-01-02	’593 Patent Issue Date
2009-12-01	’044 Patent Issue Date
2018-11-02	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,627,044, "Clock-Edge Modulated Serial Link with DC-Balance Control," Issued Dec. 1, 2009

The Invention Explained

• Problem Addressed: The patent describes the challenge of data communication in mobile devices, where conventional parallel interfaces consume significant power and space and can cause electromagnetic radiation (Compl., Ex. A, '044 Patent, col. 1:15-30). While serial links reduce the number of physical connections, prior art solutions often require a separate clock channel or a local reference clock at the receiver, which adds hardware cost and reduces design flexibility ('044 Patent, col. 1:46-55).
• The Patented Solution: The invention proposes a single-channel serial link that transmits clock, data, and control signals over a single direct current (DC) balanced differential channel. This is achieved through clock-edge modulation (CEM), also known as pulse-width modulation (PWM), where data is encoded by altering the width of clock pulses. Crucially, the system incorporates dedicated DC-balancing control signals into the modulated clock signal to maintain signal integrity over the channel ('044 Patent, Abstract; col. 2:5-12).
• Technical Importance: This technique aims to reduce pin count, power consumption, and hardware complexity in battery-powered devices by consolidating multiple signal types onto a single, robust communication link ('044 Patent, col. 1:56-62).

Key Claims at a Glance

• The complaint asserts independent claim 1.
• Claim 1 requires:
  • A signal transmitter comprising:
  • a channel node to interface with a single direct current balanced differential channel;
  • circuitry connected to the channel node, the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node,
  • wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.
• The complaint reserves the right to assert additional claims, including dependent claims 2, 8-15, and 19 (Compl. ¶15).

U.S. Patent No. 6,463,092, "System and Method for Sending and Receiving Data Signals Over A Clock Signal Line," Issued Oct. 8, 2002

The Invention Explained

• Problem Addressed: The patent identifies deficiencies in prior art data communication systems, noting that they either require separate physical lines for clock and data signals, which is inefficient, or lack a mechanism for the receiver to send signals back to the transmitter without adding significant hardware complexity and cost (Compl., Ex. B, '092 Patent, col. 2:5-21).
• The Patented Solution: The invention describes a communication system where data is embedded into a clock signal by modulating the position of the clock pulse's falling edge relative to its rising edge. The rising edge remains at a consistent interval, allowing the receiver to easily recover the primary clock timing. The specification also describes how this single transmission line can be used for bidirectional communication, allowing the receiver to send data back to the transmitter ('092 Patent, Abstract; col. 2:35-49).
• Technical Importance: This method allows for the transmission of an additional data stream alongside a clock signal on a single channel without compromising clock recovery, while also enabling a low-latency return channel, thereby reducing physical interconnects and system cost ('092 Patent, col. 2:1-4).

Key Claims at a Glance

• The complaint asserts independent claim 1.
• Claim 1 requires:
  • An apparatus for transmitting a clock signal and data signals over a signal line, the apparatus comprising a clock generator having a first input, a second input and an output,
  • the clock generator modulating a falling edge of an output signal to indicate different data values,
  • the first input of the clock generator coupled to receive a clock signal,
  • and the second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted.
• The complaint reserves the right to assert additional claims, including dependent claims 2, 5, 10, and 11 (Compl. ¶30).

U.S. Patent No. 7,158,593, "Combining a Clock Signal and a Data Signal," Issued Jan. 2, 2007

• Technology Synopsis: This patent discloses a method for combining a data signal with a clock signal for transmission over a single clock channel. The core of the invention is an encoding scheme applied to the data signal before it is combined with the clock signal. This encoding shifts the energy spectrum of the data signal to higher frequencies, away from the fundamental frequency of the clock signal. A receiver can then use a low-pass filter, such as a phase-locked loop (PLL), to easily recover the clock signal while filtering out the high-frequency data component, thereby minimizing jitter and improving signal integrity (Compl., Ex. C, '593 Patent, Abstract; col. 10:5-9).
• Asserted Claims: The complaint asserts independent claim 34 (Compl. ¶45).
• Accused Features: The complaint alleges that the UFS system in the accused product infringes by encoding data to be transmitted and multiplexing a pulse-width modulated clock signal with the encoded data signal. This encoding scheme allegedly shifts the energy spectrum of the signal to facilitate clock recovery at the receiver (Compl. ¶50).

III. The Accused Instrumentality

Product Identification

• The Sony Xperia XZ smartphone is identified as the accused product (Compl. ¶¶16, 31, 46).

Functionality and Market Context

• The infringement allegations focus on the smartphone's use of Universal Flash Storage (UFS) for its internal memory (Compl. ¶¶18, 33, 48). A screenshot from Sony's product specifications page is provided as evidence that the device contains "UFS internal memory" (Compl. ¶18).
• The complaint alleges that this UFS implementation utilizes the MIPI M-PHY protocol for the physical communication layer between the U.S. host (System-on-Chip) and the UFS device (NAND Flash memory) (Compl. ¶¶19, 34, 49).
• To support this, the complaint includes a technical diagram from a third-party white paper depicting a UFS host and device communicating via an M-PHY interface over a differential signal pair (Compl. ¶19). This diagram illustrates the core architecture accused of infringement.
• The complaint does not provide specific allegations regarding the product's market positioning beyond its identification as a smartphone.

IV. Analysis of Infringement Allegations

’044 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a channel node to interface with a single direct current balanced differential channel;	The UFS hosts and devices in the accused product contain signal transmitters that drive a DC-balanced differential signal over a communications channel.	¶20	col. 2:5-7
circuitry connected to the channel node, the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node,	The UFS transmitters are alleged to multiplex a pulse-width modulated clock signal, a data signal, and control signals to apply them to the communications channel.	¶20	col. 2:8-10
wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.	The complaint alleges that the transmitters use a "pulse-width modulated clock signal" and that this modulation is used to incorporate "DC-balancing control signals."	¶20	col. 2:10-12

• Identified Points of Contention:
  • Technical Question: The complaint alleges that the accused UFS system uses pulse-width modulation to incorporate direct current balancing control signals. The key question for the court will be an evidentiary one: what proof demonstrates that the PWM signaling in the M-PHY standard, as used by Sony, is specifically for incorporating DC-balance control signals, as required by the claim, rather than achieving DC balance through a different mechanism (e.g., a line code like 8b/10b) that is separate from the PWM function?

’092 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An apparatus for transmitting a clock signal and data signals over a signal line, the apparatus comprising a clock generator...	The UFS hosts and devices in the accused products are alleged to be such an apparatus, containing the necessary components for transmitting combined clock and data signals.	¶35	col. 2:35-37
the clock generator modulating a falling edge of an output signal to indicate different data values,	The UFS system is alleged to modulate its clock signal based on data. The complaint cites an M-PHY description mentioning PWM signaling.	¶35	col. 2:37-39
the first input of the clock generator coupled to receive a clock signal,	The technical diagram provided in the complaint shows a "Ref Clock" input to the M-PHY block, which is alleged to correspond to this limitation.	¶34	col. 4:43-47
and the second input... coupled to receive a control signal indicating a data value to be transmitted.	The same diagram shows data flowing from a Controller IP Core into the M-PHY block, which is alleged to provide the data value to be transmitted.	¶34	col. 4:47-51

• Identified Points of Contention:
  • Scope Question: A primary point of contention may arise from the claim's specific requirement of "modulating a falling edge." The '092 patent's invention is premised on preserving the rising edge for clock recovery while encoding data on the falling edge. The question for the court is whether the PWM or NRZ signaling alleged to be used in the accused M-PHY standard meets this precise limitation. The complaint's allegations are general and do not specify which edge is modulated, raising the possibility of a mismatch between the accused functionality and the claim language.

V. Key Claim Terms for Construction

For the ’044 Patent

• The Term: "direct current balancing control signals"
• Context and Importance: The infringement analysis for the '044 patent hinges on this term. The case will question whether the signals embedded via PWM in the accused device are specifically "control signals" for DC balancing, or if they are simply data bits from an encoding scheme (like 8b/10b) that happens to achieve DC balance as a secondary property.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the signals as being for the purpose of "maintain[ing] DC-balance, increas[ing] DC-balance, and decreas[ing] DC-balance" ('044 Patent, col. 3:24-26). Plaintiff may argue this covers any bits within the transmitted stream, regardless of their origin, that are manipulated to affect the running DC disparity of the line.
  • Evidence for a Narrower Interpretation: The patent provides a specific embodiment where the data bit "1" is encoded as either a 25% ("1-") or 75% ("1+") duty cycle pulse, with the choice depending on the running DC value ('044 Patent, col. 3:30-38). Defendant may argue that the term is limited to this specific mechanism of selecting between alternative encodings for a data bit to actively manage DC balance, rather than just any encoded stream that is inherently DC-balanced.

For the ’092 Patent

• The Term: "modulating a falling edge"
• Context and Importance: This term is the central limitation of the asserted claim of the '092 patent. Infringement depends entirely on whether the accused M-PHY signaling scheme falls within the scope of this phrase.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A plaintiff could argue the term should be given its plain meaning, covering any method where the falling edge of a clock pulse is moved in time to encode data, such as standard PWM signaling where the rising edge is fixed.
  • Evidence for a Narrower Interpretation: The specification repeatedly emphasizes that the invention "preserves the rising edge of the clock for clock recovery" ('092 Patent, col. 4:34-35) and describes creating discrete falling edge positions to represent bit values (see FIG. 4). A defendant may argue the term requires a specific scheme where the rising edge is kept stable as a reference, and if the accused M-PHY signaling modulates both edges or uses a different clock recovery method, it does not infringe.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all three patents under 35 U.S.C. § 271(b). The allegations are based on Sony's alleged knowledge of the patents (dating from the service of the complaint) and affirmative acts of inducement, such as creating advertisements, establishing distribution channels, and publishing user manuals for the accused Xperia XZ smartphone (Compl. ¶¶ 24, 39, 54).
• Willful Infringement: While the complaint does not use the term "willful," it requests treble damages in its prayer for relief (Compl., Prayer for Relief ¶d). The factual basis for this claim appears to be post-suit conduct, as the complaint alleges Sony has known of the infringement "at least as early as the service date of this Original Complaint" (Compl. ¶¶ 23, 38, 53).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of technical specificity and claim scope: do the industry-standard signaling protocols (MIPI M-PHY) allegedly used in the Sony Xperia XZ practice the specific methods recited in the claims? For instance, does the protocol "modulate a falling edge" while preserving the rising edge as required by the ’092 patent, and does it use PWM specifically to "incorporate direct current balancing control signals" as required by the ’044 patent?
• A second central issue will be evidentiary: the complaint relies on general statements about the accused product and technical descriptions from a third-party white paper on the UFS standard. A key question for the court will be whether the evidence presented, and that which emerges in discovery, is sufficient to prove that Sony's specific implementation of the UFS and M-PHY standards in the Xperia XZ performs each and every step of the asserted patent claims.