DCT
1:18-cv-01810
XMTT Inc v. Intel Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: XMTT, Inc. (Delaware)
- Defendant: Intel Corp (Delaware)
- Plaintiff’s Counsel: Farnan LLP
- Case Identification: 1:18-cv-01810, D. Del., 11/16/2018
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Intel is a Delaware corporation and therefore resides in the district, and because it manufactures and sells accused products within the district.
- Core Dispute: Plaintiff alleges that Defendant’s systems-on-a-chip (SoCs) containing integrated graphics technology infringe two patents related to computer architectures for hybrid serial and parallel processing.
- Technical Context: The technology addresses the challenge of designing computer processors that can efficiently switch between and coordinate serial tasks (typically handled by a main CPU) and parallel tasks (often handled by a graphics or other co-processor).
- Key Procedural History: The complaint alleges extensive pre-suit history between the inventor, Dr. Uzi Vishkin, and Intel, including multiple technical presentations at Intel facilities and discussions regarding potential collaboration or acquisition of the technology, which may be relevant to the issue of willful infringement. Subsequent to the complaint filing, U.S. Patent No. 7,707,388 was subject to an Inter Partes Review (IPR2020-00145), which concluded with a determination that all original claims (1-39) are patentable.
Case Timeline
| Date | Event |
|---|---|
| 2005-11-29 | Earliest Priority Date ('879 & '388 Patents) |
| 2008-01-01 | Inventor presentations to Defendant begin (approximate) |
| 2010-04-27 | '388 Patent Issue Date |
| 2012-03-27 | '879 Patent Issue Date |
| 2018-11-16 | Complaint Filing Date |
| 2019-11-13 | IPR Filed Against '388 Patent (IPR2020-00145) |
| 2022-11-03 | IPR Certificate Issued for '388 Patent (Claims 1-39 found patentable) |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,145,879 - Computer Memory Architecture For Hybrid Serial And Parallel Computing Systems, issued March 27, 2012
The Invention Explained
- Problem Addressed: The patent describes a problem in computer systems where "conventional approaches often do not allow for efficient execution of coordinated, mixed (i.e., 'hybrid') parallel and serial processing modes" ('879 Patent, col. 1:52-56; Compl. ¶12).
- The Patented Solution: The invention proposes a specific hardware architecture to solve this problem. It consists of a "serial processor" with its own "private memory" for serial tasks, alongside a "plurality of parallel processors" that use a separate set of "shared memory modules" for parallel tasks ('879 Patent, col. 3:51-4:10; Compl. ¶13). This partitioned structure is designed to allow programs to efficiently use both processing modes. One novel aspect is the requirement that at least one of the parallel processors has its own "local read-only memory" ('879 Patent, col. 5:9-15).
- Technical Importance: This architectural approach aims to improve the speed and power efficiency of multi-core processors by providing a structured way to manage the distinct demands of serial and parallel code execution within a single system (Compl. ¶14).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶16).
- Claim 1 requires:
- An apparatus comprising: a serial processor to execute instructions primarily in serial;
- a first, private memory to store data solely for use by the serial processor;
- a plurality of parallel processors to execute instructions primarily in parallel;
- at least one parallel processor of the plurality having a second, local read-only memory; and
- a plurality of shared memory modules to store data for use by the plurality of parallel processors.
- The complaint reserves the right to assert other claims.
U.S. Patent No. 7,707,388 - Computer Memory Architecture For Hybrid Serial And Parallel Computing Systems, issued April 27, 2010
The Invention Explained
- Problem Addressed: Like its counterpart, the '388 Patent addresses the inefficiency of "conventional approaches" in executing "hybrid" parallel and serial processing modes ('388 Patent, col. 1:45-54; Compl. ¶40).
- The Patented Solution: The '388 Patent claims a similar hybrid architecture but adds a specific method for managing the transition from serial to parallel mode. Before the transition, the serial processor must transfer updated data from its serial memory to the parallel memory modules and then "receive a corresponding acknowledgement" that the data is "queued or committed" before any parallel processors can access it ('388 Patent, col. 2:11-34; Compl. ¶41, ¶54-55). This sequence is designed to ensure "memory coherence," preventing the parallel processors from working with stale data.
- Technical Importance: This invention focuses on the critical data-synchronization step required to move from a serial to a parallel state, aiming to provide a "substantially seamless transition" while maintaining data integrity ('388 Patent, col. 2:3-5).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶44).
- Claim 1 requires:
- An apparatus comprising: a serial processor; a serial memory; a plurality of parallel processors; and a plurality of partitioned memory modules;
- wherein the serial processor is further adapted, prior to a transition from a serial to a parallel processing mode, to provide for a transfer of updated data from the serial memory to at least one of the partitioned memory modules; and
- to receive a corresponding acknowledgement from the partitioned memory module(s) that the updated data has been queued or committed prior to any memory requests from the parallel processors.
- The complaint reserves the right to assert other claims.
III. The Accused Instrumentality
- Product Identification: The accused instrumentalities are Intel "systems-on-a-chip (or 'SoCs')" that contain "Intel® Graphics Technology," including Intel Core-series processors (Compl. ¶15, ¶17, ¶43, ¶45).
- Functionality and Market Context: The complaint alleges that these SoCs embody a hybrid architecture. They contain one or more "CPU cores" that function as serial processors for general computing tasks (Compl. ¶17, ¶45). They also contain integrated graphics hardware, comprised of components called "Slices," "Subslices," and "Execution Units," which allegedly function as a "plurality of parallel processors" for tasks like graphics rendering and other parallel computations (Compl. ¶21-22, ¶49-50). The complaint includes a diagram from an Intel specification illustrating the high-level architecture of an Intel® Core™ i7 processor, showing the CPU cores and Processor Graphics components linked by a "SoC Ring Interconnect" (Compl. ¶18).
IV. Analysis of Infringement Allegations
'879 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a serial processor to execute instructions... primarily in serial | The "CPU core(s)" within the accused SoCs. | ¶17, ¶19 | col. 3:51-54 |
| a first, private memory to store data solely for use by the serial processor | The L1 and L2 caches associated with each CPU core. | ¶20 | col. 4:1-3 |
| a plurality of parallel processors to execute instructions... primarily in parallel | The graphics hardware, which includes one or more "Slices," each comprising multiple "Subslices" and "Execution Units." A diagram shows the hierarchical structure of these components (Compl. ¶22). | ¶21-22 | col. 3:55-58 |
| at least one parallel processor... having a second, local read-only memory | Each "Subslice" is identified as a parallel processor containing a "sampler," which the complaint, citing an Intel specification, alleges is a "read-only memory fetch unit." A diagram illustrates the Subslice containing EUs and a sampler (Compl. ¶23). | ¶23-24 | col. 5:9-11 |
| a plurality of shared memory modules to store data for use by the plurality of parallel processors | The "L3 Data Cache" which is shared by the graphics Slices. | ¶25-26 | col. 3:37-41 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the accused components map to the claimed terms. For example, does a "sampler" that is a "read-only memory fetch unit" meet the claim limitation of a "local read-only memory"? Further, is the L1/L2 cache truly "private" and for the "sole" use of the serial processor, as the claim requires?
- Technical Questions: The analysis may focus on how data flows between the CPU cores, their caches, the L3 cache, and the graphics execution units, to determine if the functions of the accused components align with the distinct "private" and "shared" memory structures claimed in the patent.
'388 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a serial processor | The "CPU core(s)" within the accused SoCs. | ¶45, ¶47 | col. 14:50-52 |
| a serial memory | The L1 and L2 caches associated with each CPU core. | ¶48 | col. 14:53-56 |
| a plurality of parallel processors | The graphics hardware, including "Slices," "Subslices," and "Execution Units." | ¶49-51 | col. 14:57-60 |
| a plurality of partitioned memory modules | The "L3 Data Cache," which the complaint alleges can be instantiated as multiple "L3 cache partitions." | ¶52-53 | col. 14:61-64 |
| wherein the serial processor is further adapted... to provide for a transfer of updated data... and to receive a corresponding acknowledgement... that the updated data has been queued or committed... | This allegedly occurs when a program on the CPU cores dispatches a task to the graphics hardware using libraries like OpenGL or Direct3D. Data is transferred via "buffer objects" which must be allocated and committed to memory before the parallel processors can make requests, which functionally serves as the required acknowledgement. | ¶54-57 | col. 2:11-34 |
- Identified Points of Contention:
- Scope Questions: The dispute may center on the meaning of "acknowledgement." Does the claim require a discrete, explicit signal, or can it be satisfied by the successful completion of a series of API calls (e.g., allocating and binding a buffer object) that ensures data is ready for use?
- Technical Questions: What evidence demonstrates that the standard operation of graphics APIs like OpenGL, as implemented by Intel's drivers and hardware, constitutes the specific sequence of "transfer" and "acknowledgement" claimed in the '388 Patent? The court will likely need to analyze the low-level interaction between the CPU, the graphics driver, and the graphics hardware.
V. Key Claim Terms for Construction
For the '879 Patent:
- The Term: "a first, private memory to store data solely for use by the serial processor"
- Context and Importance: The viability of the infringement allegation hinges on whether the L1/L2 caches of Intel's CPU cores meet this limitation. Practitioners may focus on this term because the word "solely" is a strong constraint, and modern processor architectures often feature complex cache coherency protocols that may allow other components to access or be affected by these caches under certain conditions.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's description of the serial memory as providing "quick access to data for serial processor 14" ('879 Patent, col. 5:9-10) could suggest the primary purpose is speed, not absolute isolation, potentially allowing for incidental or indirect access by other components.
- Evidence for a Narrower Interpretation: The claim language "solely for use by" is explicitly restrictive. The specification reinforces this, stating "only serial processor 14 can access and may write to" this memory, and that parallel processors "do not access data stored in serial memory 16" ('879 Patent, col. 4:1-5).
For the '388 Patent:
- The Term: "receive a corresponding acknowledgement... that the updated data has been queued or committed"
- Context and Importance: This term is the central, distinguishing feature of the asserted claim of the '388 Patent. The infringement case depends on whether the alleged actions in the accused products—such as API calls that allocate and bind buffer objects—can be defined as this "acknowledgement."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent explains the purpose of this step is "to ensure memory coherence" ('388 Patent, col. 2:27-28). This functional description may support an interpretation where any mechanism that ensures data is ready and coherent before parallel processing begins qualifies as an "acknowledgement," even if it is not a single, discrete signal.
- Evidence for a Narrower Interpretation: The flowchart in Figure 5 depicts "Receive a corresponding acknowledgement" as a distinct step (504) separate from the data transfer (502) ('388 Patent, Fig. 5). This could support a narrower construction requiring a specific, separate confirmation event, rather than an inferred state of readiness resulting from a series of other operations.
VI. Other Allegations
- Indirect Infringement: The complaint alleges that Intel induces infringement by providing customers with documentation, datasheets, and software developer's manuals that instruct them how to use the accused SoCs in a manner that practices the claimed inventions (Compl. ¶28, ¶59).
- Willful Infringement: The complaint makes extensive allegations to support willfulness. It claims Intel had pre-suit knowledge of the patents and the underlying technology for many years through numerous avenues, including: direct technical presentations by the inventor to Intel's chip architects; discussions with the inventor about potential collaborations; and Intel's alleged consideration of acquiring the technology. The complaint further alleges that Intel was willfully blind to the patents' existence, citing a purported corporate policy forbidding employees from reading patents held by outside companies (Compl. ¶27, ¶33, ¶58, ¶64).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural mapping: Can the plaintiff demonstrate that the components of Intel's complex, multi-purpose SoC architecture—with its hierarchical caches and integrated graphics—map cleanly onto the specific, partitioned "private memory," "local read-only memory," and "shared memory" structures required by the '879 patent?
- A key technical question will be one of functional interpretation: For the '388 patent, does the sequence of commands and state changes within standard graphics APIs (like OpenGL) for preparing data for parallel processing constitute the specific "transfer" and "acknowledgement" sequence recited in Claim 1, or does the patent require a discrete, purpose-built handshake mechanism that is absent in the accused products?
- A critical factual dispute will likely surround willfulness: Given the detailed allegations of pre-suit knowledge and interaction, the case may turn on what Intel knew about the asserted patents and when it knew it, and whether its actions constituted deliberate infringement or willful blindness.