Altair Logix LLC v. Mattel Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Mattel Inc. (Delaware)
  • Plaintiff’s Counsel: Devlin Law Firm LLC
• Case Identification: 1:18-cv-01861, D. Del., 11/26/2018
• Venue Allegations: Venue is asserted in Delaware on the basis that Defendant Mattel Inc. is a Delaware corporation and therefore resides in the district.
• Core Dispute: Plaintiff alleges that Defendant’s Nabi Elev-8 tablet, which incorporates an ARM-based multicore processor, infringes a patent related to dynamically reconfigurable circuits for media processing.
• Technical Context: The technology relates to System-on-a-Chip (SoC) architectures that use multiple, adaptable processing units to efficiently handle demanding, real-time tasks like graphics and video, which are central to modern consumer electronics.
• Key Procedural History: The complaint notes that the asserted patent’s Claim 1 issued without any amendment and that there was no rejection in the prosecution history contending the claim was anticipated by prior art.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - “Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates”

The Invention Explained

• Problem Addressed: The patent describes the trade-offs in integrated circuit design between high-performance, fixed-function hardware and more flexible but lower-performance solutions like general-purpose processors or FPGAs. Fixed-function systems suffer from "temporal redundancy," where silicon resources are dedicated to all possible functions, even if only a subset is used at any given time, increasing cost ('434 Patent, col. 2:50-57).
• The Patented Solution: The invention proposes an apparatus with a plurality of dynamically reconfigurable "media processing units." These units can be adapted at run-time to execute different computational tasks, aiming to reduce cost by re-using hardware elements without sacrificing the performance of fixed-function implementations ('434 Patent, col. 3:1-11; Abstract). Figure 3 illustrates an embodiment with eight such media processing units interconnected on a single chip ('434 Patent, Fig. 3).
• Technical Importance: The described architecture sought to combine the speed of application-specific circuits with the flexibility of programmable processors, a central challenge in the development of efficient Systems-on-a-Chip for multimedia applications ('434 Patent, col. 2:64–col. 3:1).

Key Claims at a Glance

• The complaint asserts independent Claim 1 (Compl. ¶26).
• The essential elements of Claim 1 include:
  • An addressable memory for storing data and instructions.
  • A plurality of "media processing units," each coupled to the memory.
  • Each media processing unit comprising a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit (BMU).
  • The ALU must be capable of operating concurrently with the multiplier and/or the arithmetic unit.
  • The BMU must be capable of operating concurrently with the ALU and at least one of the multiplier or arithmetic unit.
  • Each of the plurality of media processors must be capable of performing an operation simultaneously with other media processors.
  • An "operation" is defined as receiving an instruction and data from memory, processing the data, and providing a result.

III. The Accused Instrumentality

Product Identification

The Nabi Elev-8 tablet ("Accused Instrumentality") (Compl. ¶26).

Functionality and Market Context

The Nabi Elev-8 is a tablet computer marketed for children (Compl. p. 10). The complaint identifies its core processing component as the Qualcomm Snapdragon 615 processor, which is described as an octa-core processor based on the ARM Cortex-A53 architecture (Compl. ¶¶10, 28). The infringement allegations focus on the functionality of the ARM Cortex-A53 cores and their integrated NEON media coprocessor, which is alleged to perform the functions of a "media processing unit" (Compl. ¶28). The complaint alleges these processors are coupled to a memory system from which they receive instructions and data (Compl. ¶27).

IV. Analysis of Infringement Allegations

Claim Chart Summary

Identified Points of Contention

• Scope Questions: A central question for the court may be whether a general-purpose processor core (ARM Cortex-A53) with an advanced SIMD (Single Instruction, Multiple Data) coprocessor (NEON) constitutes a "media processing unit" as described in the '434 patent. The patent appears to describe a more specialized, dynamically reconfigurable architecture, raising the question of whether the claim scope covers modern multi-core CPUs.
• Technical Questions: Claim 1 requires specific concurrent operation capabilities (e.g., the bit manipulation unit operating concurrently with the ALU and multiplier). While the complaint provides block diagrams showing the existence of these functional units, the question remains whether the evidence will demonstrate that the accused architecture is "capable of operating concurrently" in the specific manner required by the claim, as opposed to merely pipelining different instruction types.

V. Key Claim Terms for Construction

The Term: "media processing unit"

Context and Importance

This term defines the fundamental building block of the claimed apparatus. The outcome of the case may hinge on whether a standard ARM Cortex-A53 processor core is considered a "media processing unit" under the patent's definition. Practitioners may focus on this term because it is the primary point of contact between the patent's 1997-era disclosure and the accused 2018-era technology.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The patent abstract describes the invention as an "apparatus and method" where processors "can operate under control of a stored program, which configures each processor," language that could be argued to encompass a modern CPU. The complaint cites the patent to define the term as the "aggregate of the dynamically reconfigurable computational and storage elements" (Compl. ¶21, citing '434 Patent, col. 3:14-18).
• Evidence for a Narrower Interpretation: The specification repeatedly emphasizes "run-time reconfigurable" circuits and "re-using groups of computational and storage elements in different configurations" to reduce cost ('434 Patent, col. 3:1-4). A defendant may argue this language limits the term to architectures with a specific type of reconfigurable fabric, distinct from a general-purpose CPU with a fixed instruction set.

The Term: "capable of operating concurrently"

Context and Importance

This limitation appears for both the arithmetic logic unit and the bit manipulation unit. Infringement requires that the accused ARM/NEON architecture has these specific parallel processing capabilities.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: A party might argue that "capable" means the hardware architecture simply allows for such concurrency, regardless of whether it is used in every software application. The complaint provides a block diagram of the accused NEON media coprocessor, identifying functional blocks such as an "Integer ALU", "Integer MUL", "FP MUL", and "FP ADD", which could be used to argue the inherent capability exists (Compl. p. 15).
• Evidence for a Narrower Interpretation: The term could be construed to require a specific type of true, simultaneous execution of operations from different units, beyond standard superscalar or pipelined execution. The patent describes an apparatus that may "execute three concurrent 32 bit arithmetic or logical operations in parallel while accessing four 32 bit data words from memory" in a single clock cycle ('434 Patent, col. 4:39-44), which could be used to argue for a very high bar for "concurrency."

VI. Other Allegations

Indirect Infringement

The complaint does not contain specific factual allegations to support claims of induced or contributory infringement. The allegations focus on direct infringement through the "making, using, selling, and offering for sale" of the accused product (Compl. ¶26).

Willful Infringement

The complaint does not include an allegation of willful infringement. It alleges only constructive notice "by operation of law," which is generally insufficient to support a willfulness claim (Compl. ¶37).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "media processing unit," which is rooted in the patent's disclosure of a dynamically reconfigurable architecture, be construed to cover a modern general-purpose ARM processor core with a fixed-function SIMD coprocessor?
• A key evidentiary question will be one of functional capability: does the accused ARM/NEON architecture possess the specific concurrent operation capabilities required by Claim 1 (e.g., a bit manipulation unit operating simultaneously with an ALU and a multiplier), and what level of proof will be required to demonstrate this capability beyond the existence of separate functional blocks in a diagram?