Invensas Corp v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Invensas Corporation (Delaware)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea) and Samsung Electronics America, Inc. (New York)
  • Plaintiff’s Counsel: Latham & Watkins LLP; Ward, Smith & Hill, PLLC
• Case Identification: 2:17-cv-670, E.D. Tex., 09/28/2017
• Venue Allegations: Venue for Samsung Electronics Co., Ltd., a foreign entity, is alleged to be proper in any judicial district. Venue for Samsung Electronics America, Inc. is alleged to be proper in the Eastern District of Texas based on its asserted "regular and established place of business" in Richardson, Texas, where it allegedly employs personnel and commits acts of infringement.
• Core Dispute: Plaintiff alleges that Defendant’s flagship mobile devices and their internal semiconductor components, such as processors and memory, infringe five patents related to methods and structures for semiconductor manufacturing and packaging.
• Technical Context: The patents relate to advanced fabrication techniques for integrated circuits, including chemical-mechanical planarization and noise isolation in chip packages, which are critical for increasing the density, performance, and reliability of modern electronics.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of the asserted patents and their alleged infringement as early as April 20, 2016. It also notes that Plaintiff has sued other Samsung affiliates on the ’231 and ’946 patents in a different district. Subsequent to the filing of this complaint, the asserted claims of the ’231 patent (claims 1-8) and the ’946 patent (claims 16-22) were cancelled in Inter Partes Review (IPR) proceedings, as reflected in certificates issued on October 3, 2023, and October 4, 2023, respectively.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,232,231 - Planarized Semiconductor Interconnect Topography and Method For Polishing a Metal Layer To Form Interconnect, issued May 15, 2001

The Invention Explained

• Problem Addressed: The patent describes how the manufacturing of multi-level integrated circuits creates uneven surface topography ("hills" and "valleys"), which can cause defects during subsequent lithography and etching steps, such as poor step coverage and incomplete etching ('231 Patent, col. 1:30-52). A particular problem is "dishing," where wide metal features are excessively polished down relative to surrounding areas during chemical-mechanical polishing (CMP) ('231 Patent, col. 2:35-41).
• The Patented Solution: The invention proposes a method to improve surface planarity by strategically adding non-functional "dummy" features. By etching a pattern of "dummy trenches" into the wide, open areas of a dielectric layer between functional interconnect trenches, the overall pattern density becomes more uniform ('231 Patent, Abstract). When these trenches are filled with metal and polished, the dummy features provide structural support to the polishing pad, preventing it from excessively flexing into and "dishing" the wide interconnects, resulting in a flatter, more uniform surface ('231 Patent, col. 5:32-44).
• Technical Importance: This method of pattern-density management allows for greater global planarity across a semiconductor wafer, a critical factor for improving manufacturing yield and enabling the reliable fabrication of complex, high-density integrated circuits ('231 Patent, col. 5:29-34).

Key Claims at a Glance

• The complaint asserts independent claim 1 ('231 Patent, col. 9:8-27; Compl. ¶19).
• Essential elements of claim 1 include:
  • Etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first (wide) trench and a series of second (narrow) trenches.
  • Filling the dummy, first, and second trenches with a conductive material.
  • Polishing the conductive material to form dummy conductors exclusively in the dummy trenches and interconnects exclusively in the first and second trenches.
  • The resulting dummy conductors are electrically separate from the underlying circuit features and co-planar with the interconnect.
• The complaint reserves the right to assert other claims, including those that depend from claim 1 (Compl. ¶19).

U.S. Patent No. 6,849,946 - Planarized Semiconductor Interconnect Topography and Method For Polishing a Metal Layer To Form Interconnect, issued February 1, 2005

The Invention Explained

• Problem Addressed: As a continuation of the application leading to the ’231 Patent, the ’946 Patent addresses the same problem of non-planar topography in semiconductor manufacturing, particularly the dishing and erosion effects associated with CMP ('946 Patent, col. 1:35-57).
• The Patented Solution: The patent claims the resulting physical structure, or topography, rather than the method of making it. The invention is a semiconductor topography that incorporates "dummy conductors" located within "dummy trenches" in a dielectric layer, positioned between a wide interconnect and a series of narrow interconnects ('946 Patent, Abstract). This structure, by its geometric arrangement, embodies a solution to the planarity problem by creating uniform pattern density ('946 Patent, col. 4:1-15).
• Technical Importance: The claimed structure provides a tangible blueprint for a semiconductor layout that inherently resists polishing defects, thereby enhancing manufacturing reliability for advanced microprocessors and other complex chips ('946 Patent, col. 4:1-6).

Key Claims at a Glance

• The complaint asserts independent claim 16 ('946 Patent, col. 10:16-47; Compl. ¶32).
• Essential elements of claim 16 include:
  • A plurality of laterally spaced dummy trenches in a dielectric layer between a first trench and a series of second trenches, with specific relative dimensional limitations.
  • Dummy conductors located in the dummy trenches that are electrically separate from features below.
  • Conductive lines (interconnects) in the first and second trenches.
  • The upper surfaces of the conductive lines are substantially coplanar with the upper surfaces of the dummy conductors.
• The complaint reserves the right to assert other claims, including those that depend from claim 16 (Compl. ¶32).

Multi-Patent Capsule: U.S. Patent No. 6,054,336

• Patent Identification: U.S. Patent No. 6,054,336, Method of Manufacturing an Electronic Device, issued April 25, 2000 (Compl. ¶12).
• Technology Synopsis: This patent discloses a method for forming very fine, closely spaced conductor patterns using a spacer-based technique. The method involves creating "auxiliary windows" in a dielectric layer that are larger than the desired final features, and then forming "spacers" on the sidewalls of these windows. These narrower spacers are then used as a mask to etch the final, high-resolution pattern into the underlying conductive layer ('336 Patent, Abstract; col. 2:1-13).
• Asserted Claims: Independent claim 1 (Compl. ¶44).
• Accused Features: The manufacturing processes for Samsung’s LPDDR4 and LPDDR4X DRAM memory, which allegedly use a similar spacer lithography technique to define conductive bitlines (Compl. ¶44-45, ¶47).

Multi-Patent Capsule: U.S. Patent No. 6,566,167

• Patent Identification: U.S. Patent No. 6,566,167, PBGA Electrical Noise Isolation of Signal Traces, issued May 20, 2003 (Compl. ¶13).
• Technology Synopsis: The patent describes a method for fabricating a two-layer Plastic Ball Grid Array (PBGA) package to reduce electrical noise or "cross talk" between signal traces. The solution involves patterning a grounded "isolation trace" on the top layer between groups of signal traces, and creating another ground structure on the bottom layer by connecting a row of solder balls to ground, thereby providing shielding ('167 Patent, Abstract; col. 2:50-56).
• Asserted Claims: Independent claim 1 (Compl. ¶58).
• Accused Features: The manufacturing method for the C3S5A0C02 image processor found in devices like the Samsung Galaxy S8, which is alleged to be a semiconductor package fabricated with such noise-isolating grounded traces (Compl. ¶58-59).

Multi-Patent Capsule: U.S. Patent No. 6,825,554

• Patent Identification: U.S. Patent No. 6,825,554, PBGA Electrical Noise Isolation of Signal Traces, issued November 30, 2004 (Compl. ¶14).
• Technology Synopsis: This patent, related to the ’167 patent, claims the resulting physical structure of the noise-isolating package. It claims a package substrate with at most two layers that includes an "isolating ground trace" on the first layer between signal traces to provide shielding, and a "second-layer isolating ground trace" on the second layer formed by a connected row of solder balls ('554 Patent, Abstract; Claim 1).
• Asserted Claims: Independent claim 1 (Compl. ¶72).
• Accused Features: The physical structure of the C3S5A0C02 image processor, which allegedly includes a two-layer substrate with the claimed noise control features, such as isolating ground traces on both layers (Compl. ¶73-74).

III. The Accused Instrumentality

• Product Identification: The accused products are Samsung's Galaxy S6, S7, S8, and Note8 mobile devices, along with their internal components, including Exynos processors, DRAM memory (LPDDR4 and LPDDR4X), and the C3S5A0C02 image processor (Compl. ¶16, ¶19, ¶44, ¶58).
• Functionality and Market Context: The complaint targets the fundamental manufacturing processes and structures of the semiconductor chips that power these high-volume, flagship smartphones (Compl. ¶16). The allegations focus on the methods used to create planar interconnect layers in processors and the structures used to provide noise shielding in DRAM and image processors (Compl. ¶20, ¶45, ¶59). The complaint cites Samsung's own press materials, indicating the commercial importance of the accused Exynos processors and other components within its smartphones (Compl. ¶16, ¶29).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

’231 Patent Infringement Allegations

’946 Patent Infringement Allegations

Identified Points of Contention:

• Evidentiary Questions (Method Claims): For the method claims of the ’231 Patent, a central question will be whether Plaintiff can produce sufficient evidence to prove that Samsung’s manufacturing process includes the specific sequence of steps recited in the claims. The complaint's allegations are based on "information and belief" and observations of the final product, which may raise questions about the ability to definitively infer the process used.
• Scope Questions (Apparatus Claims): For the apparatus claims of the ’946 Patent, the dispute may center on the scope of relative terms. The analysis will raise questions such as: What degree of flatness is required to meet the "substantially coplanar" limitation? How is "relatively narrow" measured and defined in the context of the accused products?
• Functional vs. Structural Questions: For both patents, a key point of contention may be the function of the accused "dummy" structures. A technical question for the court will be whether these structures are truly non-functional fillers as contemplated by the patent, or if they serve some other electrical purpose in Samsung's designs that would remove them from the scope of the term "dummy."

V. Key Claim Terms for Construction

• Term: "dummy trenches" / "dummy conductors" (appearing in claims of the ’231 and ’946 Patents)

  • Context and Importance: The "dummy" nature of these features is the core of the invention, as their purpose is purely structural (to aid polishing) rather than electrical. The construction of this term will be critical to determining if the accused structures, which fill space in a similar way, fall within the claim scope.
  • Intrinsic Evidence for a Broader Interpretation: The specification states that the "dummy conductors preferably serve no purpose except to improve the planarization of the interconnect level" ('231 Patent, col. 4:37-40). This language could support an interpretation where any feature whose primary or sole purpose is mechanical planarization, regardless of its specific electrical state, is a "dummy" feature.
  • Intrinsic Evidence for a Narrower Interpretation: The specification also states that the dummy conductors "do not contain transitory voltages and/or current" and are "not connected to any gate inputs or source/drain outputs" but are "most likely... connected to a power supply or ground" ('231 Patent, col. 4:40-48). This could support a narrower construction requiring the feature to be electrically inactive or tied only to a fixed potential, potentially excluding structures with other incidental electrical characteristics.

• Term: "substantially coplanar" (appearing in claims of the ’231 and ’946 Patents)

  • Context and Importance: This term defines the required outcome of the invention and the structural state of the final product. Its construction will determine the level of surface flatness an accused product must exhibit to infringe.
  • Intrinsic Evidence for a Broader Interpretation: The patent aims to solve the problem of "dishing" and "recessed" areas, which are described as significant elevational disparities ('231 Patent, col. 2:63-65). This context may support a broader interpretation where "substantially coplanar" means a surface that is largely free of the gross topographical defects the patent sought to fix, allowing for minor, commercially acceptable variations.
  • Intrinsic Evidence for a Narrower Interpretation: The figures in the patent, such as Figure 7, depict a perfectly flat, idealized final surface. A defendant could argue this illustrative embodiment implies that "substantially coplanar" requires a very high degree of planarity with minimal deviation, and any product exhibiting measurable dishing or erosion, even if reduced, does not meet the limitation.

VI. Other Allegations

• Indirect Infringement: The complaint alleges that Samsung induces infringement by actively encouraging the sale, use, and importation of the accused products through marketing materials, technical specifications, data sheets, press releases, and user manuals (Compl. ¶29, ¶41, ¶55, ¶69, ¶80). These materials allegedly promote the infringing chips and devices containing them.
• Willful Infringement: The willfulness allegations are based on alleged pre-suit knowledge. The complaint asserts that for each patent-in-suit, "Invensas disclosed the existence of the [patent] to Samsung and identified at least some of Samsung's activities that infringe" on or before April 20, 2016 (Compl. ¶27, ¶39, ¶54, ¶67, ¶78). The complaint alleges that Samsung's continued infringement despite this knowledge has been and continues to be willful (Compl. ¶28, ¶40, ¶54, ¶68, ¶79).

VII. Analyst’s Conclusion: Key Questions for the Case

• Impact of Post-Filing IPRs: A threshold issue for the counts on the ’231 and ’946 patents is the legal effect of the subsequent IPR proceedings that cancelled the asserted claims. A dispositive question will be whether these infringement counts can be maintained given that the central claims on which they rely are no longer valid.
• Proof of Process from Product: For the method-based patents ('231, '336, '167), a key evidentiary question will be one of "inference:" can the plaintiff present sufficient evidence from reverse-engineering the final products to compellingly prove that Samsung’s secretive, internal manufacturing processes perform the specific steps recited in the method claims?
• The Scope of Relative and Functional Terms: The case will likely turn on a question of "definitional scope" for apparatus claims. Can terms rooted in the patent's specific context, such as "dummy conductor," "noise control," and "substantially coplanar," be construed to read on the structures and measured performance of Samsung's accused chips, or is there a fundamental mismatch in function or degree?