DCT

1:18-cv-01966

Texasldpc Inc v. Broadcom Inc

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:18-cv-01966, D. Del., 05/04/2022 (Third Amended Complaint)
  • Venue Allegations: Venue is asserted in the District of Delaware based on Defendants being Delaware corporations, systematically transacting business in the district, and placing infringing products into the stream of commerce within the district.
  • Core Dispute: Plaintiff alleges that Defendants’ semiconductor products, including hard disk drive controllers, solid-state drive controllers, and Wi-Fi chips, infringe six patents related to efficient Low-Density Parity-Check (LDPC) decoder architectures.
  • Technical Context: Low-Density Parity-Check (LDPC) codes are a class of highly efficient error-correcting codes essential for reliable, high-speed data transmission and storage in modern digital communications and data storage systems.
  • Key Procedural History: The complaint alleges a detailed history of willful infringement, asserting that the inventor, Dr. Kiran Gunnam, developed the patented technology at Texas A&M University (TAMUS) and was subsequently hired by Defendant LSI (a Broadcom predecessor). It is alleged that Dr. Gunnam provided his designs to LSI with the express understanding that a license from TAMUS was required for commercial use, that LSI declined to take a license but proceeded to incorporate the technology into its products, and that Dr. Gunnam repeatedly notified LSI/Broadcom management of the infringing activity both before and after the patents-in-suit issued.

Case Timeline

Date Event
2007-05-01 Priority Date for all Patents-in-Suit ('320 Provisional Application)
2008-01-01 Dr. Gunnam hired by Defendant LSI
2009-08-21 LSI internal presentation on "Layered Decoder" technology
2010-01-01 LSI finalizes design for McLaren TrueStore HDD controller chip
2011-03-01 Dr. Gunnam resigns from LSI
2012-04-27 Dr. Gunnam notifies LSI of pending patent applications
2013-01-22 U.S. Patent No. 8,359,522 Issues
2013-08-09 U.S. Patent No. 8,418,023 Issues
2013-10-08 U.S. Patent No. 8,555,140 Issues
2014-01-31 Dr. Gunnam notifies LSI of issued '023 and '140 Patents
2014-02-18 U.S. Patent No. 8,656,250 Issues
2015-08-18 U.S. Patent No. 9,112,530 Issues
2018-11-27 U.S. Patent No. 10,141,950 Issues
2022-05-04 Third Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,418,023 - "Low Density Parity Check Decoder For Irregular LDPC Codes"

The Invention Explained

  • Problem Addressed: The patented technology addresses inefficiencies in prior art Low-Density Parity-Check (LDPC) decoders, which are described as being slower, larger, and less power-efficient than desired for high-data-rate applications (Compl. ¶55). These prior designs allegedly suffered from high memory usage and performed redundant calculations (Compl. ¶55).
  • The Patented Solution: The invention provides an improved LDPC decoder architecture that uses "on-the-fly computation" and "out-of-order" processing of data blocks within a matrix to reduce memory requirements, eliminate pipeline idle cycles, and resolve memory access conflicts common in conventional decoders (’023 Patent, Abstract; Compl. ¶72). This approach allows for the scheduling of message computations for different data blocks to occur concurrently, improving processing throughput (’023 Patent, col. 4:45-67).
  • Technical Importance: This architectural improvement allowed digital electronic devices to transmit data over noisy channels at substantially higher rates, enabling more efficient performance in technologies like hard disk drives, flash memory, and Wi-Fi (Compl. ¶54).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 18 (Compl. ¶¶125-126, 136).
  • The essential elements of independent claim 1 include:
    • A low density parity check code decoder comprising a control unit.
    • The control unit is configured to cause the decoder to process blocks of an LDPC matrix "out of order."
    • The control unit schedules the computation of "R messages" for a first block and "P and Q messages" for a second block.
    • This scheduling occurs such that the R messages for the first block are generated while processing the second block.
    • The scheduling is based on a determination of need for the R messages for the computation of P and Q messages for the second block.
    • The first and second non-zero blocks are in the same column of the matrix.
  • The complaint reserves the right to assert dependent claims 2-17 and 19-30 (Compl. ¶124).

U.S. Patent No. 8,555,140 - "Low Density Parity Check Decoder For Irregular LDPC Codes"

The Invention Explained

  • Problem Addressed: Similar to the ’023 Patent, this invention is directed at overcoming performance limitations in conventional LDPC decoders related to processing efficiency and resource utilization (’140 Patent, col. 1:26-34; Compl. ¶55).
  • The Patented Solution: The patent describes a method for decoding an LDPC code by processing data blocks in distinct sequences. It specifies a "first sequence" for processing blocks and a "second sequence" for computing "R messages" (’140 Patent, col. 30:5-10). The method further involves partitioning blocks within a given processing "layer" into a first set that is not dependent on a previously processed layer and a second set that is dependent, allowing for more efficient, ordered processing that avoids pipeline stalls (’140 Patent, col. 30:11-18).
  • Technical Importance: By defining processing sequences based on data dependencies between layers, this method enables a more structured and efficient pipeline, which is critical for achieving high throughput in hardware decoder implementations (Compl. ¶54).

Key Claims at a Glance

  • The complaint asserts independent claims 7 and 18 (Compl. ¶¶158-159, 164).
  • The essential elements of independent claim 7 include:
    • A method for decoding an LDPC code.
    • Processing blocks of an LDPC matrix in a "first sequence."
    • Computing "R messages" for the blocks in a "second sequence" that is different from the first.
    • Specifying, via the first sequence, a first set of blocks to be processed at a given time and a second set to be processed after the first set.
    • The first set specifies only blocks not dependent on a result of a previously processed layer.
    • The second set specifies blocks that are dependent on a result of the previously processed layer.
  • The complaint reserves the right to assert dependent claims 8-12 and 19-22 (Compl. ¶157).

U.S. Patent No. 9,112,530 - "Low Density Parity Check Decoder"

  • Technology Synopsis: The patent relates to an LDPC decoder architecture featuring specific hardware units. These include a Q message generator, logic for reducing the magnitude of a Q message, and a "permuter" for reordering P messages based on the processing of different blocks in the same column of an LDPC matrix (’530 Patent, col. 32:2-15). This structure aims to optimize the computational flow within the decoder.
  • Asserted Claims: Independent claims 13 and 25 (Compl. ¶¶191, 200).
  • Accused Features: The accused Hard Disk Controller, SandForce, and Densbits products are alleged to infringe by incorporating the claimed Q message generator, logic, and permuter architecture (Compl. ¶¶192-198).

U.S. Patent No. 8,359,522 - "Low Density Parity Check Decoder For Regular LDPC Codes"

  • Technology Synopsis: This patent describes a method for LDPC decoding involving specific steps for message generation and updating. The method includes selecting an "R message" based on an index and sign bit, combining it with a "P message" to generate a "Q message," cyclically shifting the P message, and updating the P message based on the final state of a block row (’522 Patent, col. 32:3-12). This sequence of operations is designed to efficiently manage the iterative message-passing process.
  • Asserted Claims: Independent claim 85 (Compl. ¶222).
  • Accused Features: All categories of Accused Products, including the Wi-Fi products, are alleged to practice the claimed method of selecting, generating, shifting, and updating messages (Compl. ¶¶223-229).

U.S. Patent No. 8,656,250 - "Low Density Parity Check Decoder For Irregular LDPC Codes"

  • Technology Synopsis: This patent claims a decoder with specific hardware units: an "R select unit," a "Q message memory" for storing a Q message until an R message is generated, and a "permuter" that permutes the P message based on the difference in permutation between a currently processed block and a previously processed block in the same column (’250 Patent, col. 32:2-15). It also claims a check node unit with a number of comparators less than the check node degree.
  • Asserted Claims: Independent claims 1, 17, 32, and 41 (Compl. ¶¶246, 253, 261, 267).
  • Accused Features: The Accused Products are alleged to contain the claimed R select unit, Q message memory, permuter, and efficient check node unit architecture (Compl. ¶¶247-275).

U.S. Patent No. 10,141,950 - "Low Density Parity Check Decoder"

  • Technology Synopsis: This patent claims a decoder with a control unit configured to process blocks of a layer "out of order" using a series of processing "substeps." These substeps include an "R new update substep," an "R old update substep," P and Q message substeps, and a "partial state substep" for updating the state of a block row based on computed Q messages (’950 Patent, col. 33:57-col. 34:24). This defines a specific, fine-grained pipeline for decoder operations.
  • Asserted Claims: Independent claims 1 and 9 (Compl. ¶¶294, 305).
  • Accused Features: The accused Hard Disk Controller, SandForce, and Densbits products are alleged to have decoding circuitry and control units that perform the claimed sequence of processing substeps (Compl. ¶¶295-311).

III. The Accused Instrumentality

Product Identification

  • The complaint names four categories of accused products: Accused Hard Disk Controller Products (including LSI's "McLaren" and "Spyder" chip families), Accused SandForce Products (SSD flash controllers), Accused Densbits Products (SSD controllers), and Accused Wi-Fi Products (a broad list of Broadcom Wi-Fi chipsets, e.g., BCM4350) (Compl. ¶¶75, 101, 107, 119, 121).

Functionality and Market Context

  • The accused products are semiconductor chips that implement LDPC decoder technology for error correction in data storage devices (HDDs and SSDs) and wireless communication devices (Wi-Fi clients and access points) (Compl. ¶¶54, 97, 108). The complaint alleges that the foundational architecture for these products was developed internally at LSI/Broadcom as the "McLaren LDPC decoder" and that this design incorporates the patented technology (Compl. ¶¶63, 75, 101). The complaint further alleges that internal LSI analysis concluded that there were "no viable alternatives" to the patented design, which offered superior performance in terms of circuit area and error correction effectiveness (Compl. ¶¶69-70). The image from an internal LSI presentation describes the "McLaren LDPC Decoder Re-Evaluation," showing other design options as "Not Feasible" due to area penalties or performance loss (Compl. p. 19).

IV. Analysis of Infringement Allegations

’023 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a low density parity check code decoder, comprising: a control unit that controls decoder processing... The accused products include an LDPC decoder with a control unit. This is evidenced by an LSI presentation describing the "McLaren Client Server Architecture" which references an LDPC decoder (Compl. p. 32). ¶127 col. 1:19-21
...cause the decoder to process blocks of a low density parity check (“LDPC”) matrix out of order... The accused decoders process blocks out of order. An LSI presentation on the "Layered Decoder" architecture explicitly references "out of order processing" (Compl. p. 33). ¶129 col. 2:6-7
...schedule computation of R messages for a first non-zero block and computation of P messages and Q messages for a second non-zero block... The accused decoders schedule computations for R, P, and Q messages for different non-zero blocks. An LSI presentation shows this scheduling for "R SELECTION" and "PS PROCESSING" (Compl. p. 36). ¶133 col. 4:45-52
...such that R messages for the first non-zero block are generated while processing the second non-zero block based on a determination of need for the R messages for the computation of P and Q messages for the second non-zero block... The accused decoders generate R messages for one block while processing another. An LSI presentation states "R selection is out-of-order so that it can feed the data required for the PS processing" (Compl. p. 37). ¶134 col. 4:53-61
...wherein the first non-zero block and the second non-zero block are in a same column of the matrix. In the accused products' operation, the first and second non-zero blocks are in the same column of the matrix, as shown in a matrix diagram from an LSI presentation (Compl. p. 38). ¶135 col. 4:62-67
  • Identified Points of Contention:
    • Scope Questions: The case may turn on the construction of "out of order." Does this term require a specific type of non-sequential processing described in the patent's embodiments, such as the "layered decoder" architecture, or does it cover any processing that is not strictly sequential? The complaint uses a side-by-side comparison of the patent's FIG. 12 and an LSI presentation slide titled "Layered Decoder, Arch 1," suggesting the patentee's infringement theory is closely tied to this specific architecture (Compl. ¶130).
    • Technical Questions: A key evidentiary question is whether the final, commercial accused products implement the exact architecture shown in the 2009-era LSI presentations. The complaint alleges the "layered decoder architecture of the Accused...Products is identical in relevant respects to what is set forth in the '023 Patent" (Compl. ¶130), but Defendants may argue that the designs evolved and the shipping products differ materially from these early presentations.

’140 Patent Infringement Allegations

Claim Element (from Independent Claim 7) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for decoding a low density parity check (LDPC) code, comprising: processing blocks of an LDPC matrix in a first sequence; computing R messages for the blocks in a second sequence that is different from the first sequence... The accused products process blocks and compute R messages in different sequences. An LSI presentation diagram shows "PS processing" following one sequence and "R selection" occurring out-of-order in a different sequence. ¶161 col. 30:5-10
...specifying, via the first sequence, a first set of blocks of a given layer to be processed at a given time and a second set of blocks of the given layer to be processed after the first set of blocks... The accused products specify sets of blocks for processing based on dependency. The complaint provides an LSI presentation slide showing this scheduling (Compl. p. 48). ¶163 col. 30:11-14
...wherein the first set specifies only blocks of the given layer that are not dependent on a result of a previously processed layer and the second set specifies blocks of the given layer that are dependent on a result of the previously processed layer. The accused products process blocks that depend on a previous layer last. An LSI presentation slide titled "Out-of-order block processing for Partial State" states "the blocks which depend on layer 1 will be processed last." ¶163 col. 30:14-18
  • Identified Points of Contention:
    • Scope Questions: The central construction issue for this patent will likely be the term "dependent." How is this dependency determined, and what specific processing constraints does it impose? The patent's definition of how blocks are partitioned into "dependent" and "not dependent" sets will be critical to defining the scope of infringement.
    • Technical Questions: The infringement allegation relies heavily on diagrams from an LSI "Layered Decoder Presentation" (Compl. ¶¶161-163). A point of contention will be the degree to which these presentation materials accurately reflect the technical operation of the multitude of accused HDD, SSD, and Wi-Fi products sold over many years.

V. Key Claim Terms for Construction

The Term: "process blocks of a low density parity check ('LDPC') matrix out of order" (’023 Patent, Claim 1)

  • Context and Importance: This term is the foundational step of the asserted claims of the ’023 patent. Its construction will determine whether the accused decoders, which allegedly employ a "layered" processing scheme, fall within the claim scope. Practitioners may focus on this term because the complaint's evidence directly links the accused products to an architecture explicitly described as supporting "out-of-order processing" (Compl. ¶129).
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states that the control unit is "configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order" without tying this capability to a single, specific algorithm, which may suggest any non-sequential processing is covered (’023 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The detailed description heavily features a "layered decoding" approach where "out-of-order" processing is explained in the specific context of scheduling message computations across different layers to improve pipeline efficiency (’023 Patent, col. 4:45-67; FIG. 12). This may support an interpretation that limits the term to this specific layered context.

The Term: "dependent on a result of a previously processed layer" (’140 Patent, Claim 7)

  • Context and Importance: This limitation defines the core logic of the claimed method: separating blocks into two sets based on their dependency on prior calculations. The infringement analysis for the ’140 patent hinges on whether the accused products perform this specific dependency-based scheduling.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not specify how the dependency is determined, potentially allowing for any method where the processing order of some blocks is contingent on the results from a prior layer.
    • Evidence for a Narrower Interpretation: The specification describes specific embodiments where dependency relates to the structure of the LDPC matrix and the flow of "check-node" and "variable-node" messages between layers (’140 Patent, col. 4:45-67). This could be used to argue that "dependent" requires this specific type of message-passing relationship, not just any logical dependency.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement by asserting that Defendants sell the accused chips to customers with the knowledge and intent that they will be incorporated into infringing end-user products (e.g., hard drives, Wi-Fi routers) sold in the U.S. (Compl. ¶143). Specific alleged acts of inducement include providing technical support, marketing materials, and co-branding, such as authorizing customers to use a "Built on BROADCOM" mark (Compl. ¶¶387, 390). Contributory infringement is alleged on the basis that the accused LDPC decoders are a material part of the claimed inventions and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶145).
  • Willful Infringement: Willfulness is alleged based on extensive pre-suit and post-suit knowledge. The complaint alleges that the inventor, Dr. Gunnam, while an employee at LSI, repeatedly informed LSI management of the TAMUS patent applications and the need for a license (Compl. ¶¶60, 76). After leaving LSI and after the patents began to issue, Dr. Gunnam allegedly continued to send emails to LSI/Broadcom executives, identifying the specific issued patents and the infringing products (Compl. ¶¶80, 86, 90). The complaint alleges these warnings were ignored and that LSI management reprimanded Dr. Gunnam for documenting the potential infringement (Compl. ¶77).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A primary evidentiary question will be one of design continuity: to what extent do the accused commercial products, sold across various product lines and over many years, implement the specific decoder architectures depicted in the 2009-era internal LSI presentations on which the infringement allegations heavily rely?
  • A central legal issue will be one of definitional scope: how broadly will the court construe terms like "out of order" and "dependent," which will determine whether Defendants' specific layered decoding and message-passing schedulers fall within the claims' boundaries?
  • Given the detailed allegations of the inventor's repeated pre-suit notifications to management, a critical question for willfulness will be the defendants' state of mind: can the plaintiff establish that the defendants acted with objective recklessness regarding patents they allegedly knew covered the core of their LDPC technology?