DCT
1:18-cv-02057
Altair Logix LLC v. Caterpillar Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: Caterpillar Inc. (Delaware)
- Plaintiff’s Counsel: Devlin Law Firm LLC
- Case Identification: [Altair Logix LLC](https://ai-lab.exparte.com/party/altair-logix-llc) v. [Caterpillar Inc.](https://ai-lab.exparte.com/party/caterpillar-inc), 1:18-cv-02057, D. Del., 12/27/2018
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Caterpillar Inc. is incorporated in Delaware.
- Core Dispute: Plaintiff alleges that Defendant’s Caterpillar CAT S41 smartphone, which incorporates a MediaTek processing unit, infringes a patent related to dynamically reconfigurable digital circuits for media processing.
- Technical Context: The technology concerns system-on-a-chip (SoC) processor architectures designed to offer the performance of fixed-function hardware with greater flexibility and lower cost for tasks like graphics and video processing.
- Key Procedural History: The complaint notes that the asserted claim (Claim 1) was an originally filed claim that issued without any amendment or prior art rejection, a point Plaintiff may use to argue for the claim's patentable distinctiveness.
Case Timeline
| Date | Event |
|---|---|
| 1997-02-28 | U.S. Patent No. 6,289,434 Priority Date |
| 2001-09-11 | U.S. Patent No. 6,289,434 Issue Date |
| 2016-01-01 | MediaTek Helio P20 MT6757 SoC introduced (approximate) |
| 2018-12-27 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,289,434 - “Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates,”
Issued September 11, 2001
The Invention Explained
- Problem Addressed: The patent addresses the trade-offs between different methods of implementing complex functions on an integrated circuit. Traditional hard-wired, fixed-function circuits offer high performance but are inflexible and costly due to "temporal redundancy"—implementing logic for all possible functions regardless of the current task (’434 Patent, col. 1:42-47, col. 2:50-60). Conversely, more flexible approaches using general-purpose microprocessors, Digital Signal Processors (DSPs), or Field Programmable Gate Arrays (FPGAs) suffer from performance or cost-effectiveness penalties for real-time media tasks (’434 Patent, col. 2:1-33).
- The Patented Solution: The invention proposes an apparatus with multiple "media processing units" (MPUs) that can be dynamically reconfigured at runtime. This architecture aims to reduce cost by re-using computational elements for different tasks as needed and employing efficient memory, thereby achieving the performance of fixed-function systems at a lower cost (’434 Patent, col. 3:1-11). The system is built around a memory map where all reconfiguration and data routing is managed, allowing for a flexible, high-performance system-on-a-chip (’434 Patent, col. 3:28-38).
- Technical Importance: The invention describes a parallel, reconfigurable architecture intended to provide a cost-effective solution for the growing computational demands of real-time media processing in the late 1990s, such as 3D graphics and video processing (’434 Patent, col. 1:32-38).
Key Claims at a Glance
- The complaint asserts infringement of Claim 1 (’434 Patent, col. 55:21-56:33; Compl. ¶26).
- Independent Claim 1 requires:
- An addressable memory for storing data and instructions.
- A plurality of media processing units, each having an input/output coupled to the memory.
- Each media processing unit comprising a multiplier, an arithmetic unit, an arithmetic logic unit, and a bit manipulation unit, each with specified inputs and outputs.
- The arithmetic logic unit being capable of operating concurrently with the multiplier and arithmetic unit.
- The bit manipulation unit being capable of operating concurrently with the arithmetic logic unit and at least one of the multiplier or arithmetic unit.
- Each of the plurality of media processors being capable of performing an operation simultaneously with other media processors.
- Each operation comprising receiving an instruction and data from memory, processing the data, and providing a result.
III. The Accused Instrumentality
Product Identification
The Caterpillar CAT S41 smartphone ("Accused Instrumentality"), which contains a MediaTek Helio P20 MT6757 System-on-a-Chip (SoC) (Compl. ¶¶ 26-27).
Functionality and Market Context
- The complaint alleges the MediaTek MT6757 SoC is the infringing component. This SoC is described as an upper-mainstream processor for Android-based smartphones, manufactured on a 16nm FinFET process and introduced in 2016 (Compl. ¶20, p. 11).
- The core of the infringement theory focuses on the SoC's multicore architecture. The complaint identifies the SoC as having eight ARM Cortex-A53 CPU cores, which it equates to the claimed "plurality of media processing units" (Compl. ¶27).
- The complaint further alleges that each ARM Cortex-A53 processor includes a NEON media coprocessor, which allegedly contains the functional sub-units (multiplier, arithmetic unit, etc.) required by the claims (Compl. ¶29). A marketing specification sheet for the Helio P20 is provided, highlighting its "8x Cortex-A53" CPU configuration and its memory capabilities (Compl. ¶28, p. 10).
IV. Analysis of Infringement Allegations
Claim Chart Summary
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs... | The Accused Instrumentality has a memory system coupled to the multicore ARM processors, which stores data and instructions and communicates via multiple internal inputs/outputs. | ¶28 | col. 55:21-27 |
| a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs | The Accused Instrumentality comprises multiple ARM Cortex-A53 multicore processors, each of which acts as a media processing unit and is coupled to the memory system. | ¶29 | col. 55:28-30 |
| each media processing unit...comprising: a multiplier... | Each processor includes a NEON media coprocessor which comprises a multiplier (e.g., Integer MUL or FP MUL). | ¶30 | col. 55:31-36 |
| an arithmetic unit... | Each processor includes a NEON media coprocessor which comprises an arithmetic unit (e.g., an FP ADD). | ¶31 | col. 55:37-42 |
| an arithmetic logic unit...capable of operating concurrently with at least one selected from the multiplier and arithmetic unit | Each processor includes a NEON media coprocessor with an arithmetic logical unit (e.g., an Integer ALU), which is alleged to be capable of operating concurrently with the multiplier and arithmetic unit. The complaint presents a diagram of the NEON pipeline showing these distinct units (Integer ALU, Integer MUL, FP ADD) to support this. | ¶32, p. 18 | col. 55:43-50 |
| a bit manipulation unit...capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit | The NEON media coprocessor allegedly contains an integer shift unit that acts as the bit manipulation unit and is capable of concurrent operation with the other units. | ¶33 | col. 55:51-56:2 |
| each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units | The Accused Instrumentality has multiple ARM Cortex-A53 processors that allegedly perform operations simultaneously with other ARM Cortex-A53 processors on the same chip. A block diagram shows the multicore architecture to support this allegation. | ¶34, p. 12 | col. 56:21-24 |
| each operation comprising: receiving...an instruction and data from memory...processing the data...to produce at least one result, and providing...the...result at the media processor input/output | Each ARM Cortex-A53 processor with its NEON coprocessor is alleged to receive instructions and data from memory, process it, and produce a result. A diagram of the NEON pipeline illustrates the flow of instructions and data. | ¶35, p. 22 | col. 56:26-33 |
Identified Points of Contention
- Scope Questions: A central question will be whether the combination of a general-purpose ARM Cortex-A53 core and its associated NEON coprocessor constitutes a "media processing unit" as that term is defined and described in the patent. The patent appears to describe a more bespoke, specialized MPU architecture (’434 Patent, Fig. 3), whereas the accused product uses a widely licensed, general-purpose CPU architecture.
- Technical Questions: The complaint alleges the various units (ALU, multiplier, etc.) are "capable of operating concurrently." This raises a key evidentiary question: does the complaint provide sufficient technical evidence that the accused ARM/NEON architecture actually operates with the specific type and degree of concurrency required by the claims, or does it merely point to the existence of separate functional blocks within a processor pipeline? The court will need to determine if the functions operate concurrently as claimed, or merely in a pipelined but sequential fashion.
V. Key Claim Terms for Construction
"media processing unit"
- Context and Importance: This term is the fundamental building block of the claimed apparatus. Its construction will determine whether a general-purpose CPU core (like the ARM Cortex-A53) falls within the scope of the claims, or if the claims are limited to a more specialized architecture. The infringement case hinges on mapping the features of the accused ARM processors onto the definition of this term.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A plaintiff might argue that the term should be defined functionally by its components. Claim 1 itself defines the MPU by what it comprises: a multiplier, an arithmetic unit, an ALU, and a bit manipulation unit (’434 Patent, col. 55:31-56:2). If the accused ARM core contains these functional blocks, it could be argued to meet the definition regardless of its overall architectural design.
- Evidence for a Narrower Interpretation: A defendant may argue that the specification provides a more limited definition. The patent repeatedly describes the invention as an alternative to general-purpose processors, DSPs, and FPGAs (’434 Patent, col. 2:1-33). The detailed description and figures (e.g., Fig. 3) illustrate a specific architecture of interconnected, reconfigurable MPUs that is structurally different from a standard multi-core CPU. This context may support a narrower construction that excludes general-purpose processors.
"capable of operating concurrently"
- Context and Importance: This functional limitation appears twice in Claim 1 and is crucial for distinguishing the invention from a simple sequential processor. The infringement analysis will turn on whether the accused processor's pipelined execution constitutes the claimed "concurrency."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Plaintiff may argue "concurrently" should be given its plain and ordinary meaning, which could encompass parallel execution within a single clock cycle or simultaneous operation of different hardware units in a superscalar or pipelined architecture. The complaint's reliance on diagrams showing distinct functional units within the NEON pipeline supports this view (Compl. p. 18).
- Evidence for a Narrower Interpretation: Defendant may argue that the patent specification, when read as a whole, implies a more specific form of parallelism than standard pipelining. The patent describes executing "three concurrent 32 bit arithmetic or logical operations in parallel while accessing four 32 bit data words from memory...all this in a single clock cycle" (’434 Patent, col. 4:39-44). This language could support a narrower construction requiring a specific, highly parallel operation within a single cycle, which may be different from the operation of the accused processors.
VI. Other Allegations
The complaint does not provide sufficient detail for analysis of indirect or willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "media processing unit," which the patent contrasts with general-purpose processors, be construed to read on the accused ARM Cortex-A53 general-purpose CPU cores? The outcome will likely depend on whether the court adopts a functional definition based on the presence of sub-components or a structural one based on the patent's overall architectural disclosure.
- A key evidentiary question will be one of functional operation: does the complaint provide sufficient technical evidence to demonstrate that the accused processor's functional units are "capable of operating concurrently" in the specific manner required by the claims? The dispute will likely focus on whether the accused product's pipelined or superscalar execution meets the threshold for concurrency described and claimed in the patent.