DCT

1:19-cv-00169

Super Interconnect Tech LLC v. HP Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-00169, D. Del., 01/29/2019
  • Venue Allegations: Venue is asserted on the basis that Defendant HP Inc. is a Delaware corporation and therefore resides in the District of Delaware.
  • Core Dispute: Plaintiff alleges that Defendant’s detachable personal computers equipped with Universal Flash Storage (UFS) infringe three patents related to methods for transmitting clock, data, and control signals over a single high-speed serial link.
  • Technical Context: The technology at issue addresses high-speed data transmission in compact electronic devices, where minimizing the number of physical communication lines is critical for reducing power consumption, cost, and electromagnetic interference.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
1998-09-10 U.S. Patent No. 6,463,092 Priority Date
2001-03-16 U.S. Patent No. 7,158,593 Priority Date
2002-10-08 U.S. Patent No. 6,463,092 Issued
2005-10-31 U.S. Patent No. 7,627,044 Priority Date
2007-01-02 U.S. Patent No. 7,158,593 Issued
2009-12-01 U.S. Patent No. 7,627,044 Issued
2019-01-29 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,627,044 - “Clock-Edge Modulated Serial Link with DC-Balance Control,” issued Dec. 1, 2009

The Invention Explained

  • Problem Addressed: The patent addresses the need for low-power, single-channel serial links in battery-powered mobile devices to transmit clock, data, and control signals without requiring separate, dedicated channels, which increase hardware costs and power consumption (’044 Patent, col. 1:15-55).
  • The Patented Solution: The invention describes a signal transmitter that uses clock-edge modulation, also known as pulse-width modulation (PWM), to encode data onto a periodic clock signal. This is achieved by varying the position of a clock edge (e.g., the falling edge) relative to a fixed edge (e.g., the rising edge) (’044 Patent, Abstract; col. 3:4-14). Crucially, the system incorporates direct current (DC) balancing control signals directly into this modulated stream to maintain signal integrity over the channel (’044 Patent, col. 3:20-28).
  • Technical Importance: This technique enables the consolidation of multiple signal types onto a single, low-power differential channel, a key requirement for designing compact and power-efficient mobile electronics.

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2, 8-15, and 19 (Compl. ¶12).
  • Independent Claim 1 recites a signal transmitter with the following essential elements:
    • A channel node to interface with a single direct current balanced differential channel.
    • Circuitry connected to the channel node.
    • The circuitry is configured to multiplex clock, data, and control signals and apply them to the channel node.
    • The clock signal is pulse width modulated to incorporate direct current balancing control signals.

U.S. Patent No. 6,463,092 - “System and Method for Sending and Receiving Data Signals Over A Clock Signal Line,” issued Oct. 8, 2002

The Invention Explained

  • Problem Addressed: The patent identifies the inefficiency and latency of using primary data channels to send control signals, as well as the lack of a return communication channel from a receiver to a transmitter in many high-speed link designs (’092 Patent, col. 1:45-63, col. 2:6-10).
  • The Patented Solution: The invention discloses a system where data is encoded onto a clock signal by modulating the position of the falling edge, while the rising edge is preserved for clock recovery at the receiver (’092 Patent, col. 4:27-36). This allows data to be transmitted over the clock line itself. The system also describes a bidirectional link, enabling the receiver to superimpose its own signals back onto the same line for return communication (’092 Patent, Abstract).
  • Technical Importance: By embedding data within the clock signal, this method increases effective bandwidth and provides a low-latency backchannel without adding physical wires, offering a more efficient interconnect solution.

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2, 5, 10, and 11 (Compl. ¶27).
  • Independent Claim 1 recites an apparatus for transmitting a clock and data signal, with the following essential elements:
    • A clock generator having a first input, a second input, and an output.
    • The clock generator modulates a falling edge of an output signal to indicate different data values.
    • The first input is coupled to receive a clock signal.
    • The second input is coupled to receive a control signal indicating the data value to be transmitted.

U.S. Patent No. 7,158,593 - “Combining a Clock Signal and a Data Signal,” issued Jan. 2, 2007

Technology Synopsis

This patent describes a method for combining clock and data signals onto a single transmission channel by first encoding the data signal to shift its energy spectrum to higher frequencies, away from the fundamental frequency of the clock signal (’593 Patent, col. 1:57-65). This spectral separation allows a clock recovery circuit at the receiver, such as a phase-locked loop (PLL) acting as a low-pass filter, to more effectively isolate the clock signal from the data-induced jitter, thereby improving signal integrity (’593 Patent, Abstract).

Asserted Claims

The complaint asserts independent claim 34 and dependent claim 35 (Compl. ¶42).

Accused Features

The complaint alleges that the UFS hosts and devices in the accused products utilize an encoding scheme that shifts the energy spectrum of the combined clock and data signal away from the loop bandwidth of a clock recovery block, thereby practicing the patented invention (Compl. ¶47).

III. The Accused Instrumentality

Product Identification

The complaint identifies the HP Envy x2 detachable PC as an exemplary accused product (Compl. ¶¶12, 27, 42).

Functionality and Market Context

  • The infringement allegations center on the product's inclusion of Universal Flash Storage (UFS) (Compl. ¶12). A screenshot of the product's specification sheet is provided as evidence that it contains "128 GB UFS storage" (Compl. ¶15).
  • The complaint alleges that the UFS storage subsystem utilizes the MIPI M-PHY protocol for its physical layer communication (Compl. ¶16). To support this, the complaint provides a diagram from a third-party white paper illustrating the interface between a UFS Host and a UFS Device via an M-PHY layer (Compl. ¶16). The complaint further specifies that the UFS standard calls for M-PHY Type 1, which uses pulse-width modulation (PWM) signaling for low-speed modes (Compl. ¶16).

IV. Analysis of Infringement Allegations

’044 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a signal transmitter... The UFS hosts and devices included in the ’044 Accused Products contain signal transmitters (Compl. ¶17). ¶17 col. 1:7-9
...comprising: a channel node to interface with a single direct current balanced differential channel; These transmitters drive a DC-balanced differential signal for a communications channel, comprised of a positive and a negative data signal (Compl. ¶17). ¶17 col. 2:1-4
circuitry... configured to multiplex clock, data and control signals... The transmitters multiplex a pulse-width modulated clock signal, a data signal, and control signals to apply them to the communications channel (Compl. ¶17). ¶17 col. 2:9-12
wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals. The complaint alleges that the accused UFS storage uses the MIPI M-PHY protocol, which uses PWM signaling (Compl. ¶16), and that the transmitters multiplex a PWM clock signal onto a DC-balanced channel (Compl. ¶17). The complaint does not specify how DC-balancing control signals are incorporated. ¶16-17 col. 2:12-14

’092 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
An apparatus for transmitting a clock signal and data signals over a signal line... The UFS hosts and devices in the ’092 Accused Products are identified as the infringing apparatus (Compl. ¶32). ¶32 col. 4:55-58
...the apparatus comprising a clock generator... modulating a falling edge of an output signal to indicate different data values... The complaint alleges that the accused products multiplex clock and data signals, and that the "clock signal is modulated based on the data to be transmitted" (Compl. ¶32). A diagram showing M-PHY I/O using PWM signaling is provided (Compl. ¶31). ¶32 col. 4:27-33

Identified Points of Contention

  • Scope Questions: The infringement allegations for all three patents rely on the functionality of the industry-standard UFS/M-PHY interface. A central question will be whether the operation of this standard, as described in the complaint, falls within the specific scope of the patent claims. For instance, does the general "modulation" alleged for the '092 patent meet the specific "modulating a falling edge" limitation?
  • Technical Questions: For the '044 patent, the complaint alleges the accused product uses PWM and that the channel is DC-balanced, but it does not explicitly allege facts showing that the PWM is the mechanism used to incorporate DC-balancing control signals, as required by the claim. The case may turn on whether Plaintiff can produce evidence linking these two functions. Similarly, for the '593 patent, the court will require evidence that the encoding used in the accused M-PHY layer in fact "shifts an energy spectrum" in the manner claimed.

V. Key Claim Terms for Construction

For the ’044 Patent:

  • The Term: "direct current balancing control signals" (Claim 1)
  • Context and Importance: This term is central to infringement. The complaint alleges the accused device has a "DC-balanced differential signal" and separately uses "pulse-width modulated clock signal," but the claim requires the latter to be the mechanism for incorporating the former. The definition of what constitutes a "control signal" for DC balancing, versus merely a DC-balanced encoding scheme, will be critical.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states that "Standard techniques are used to generate and process the DC-balance control signals" (’044 Patent, col. 3:25-28), which a party might argue supports a broad interpretation covering any conventional method of achieving DC balance via signaling.
    • Evidence for a Narrower Interpretation: The patent provides a specific embodiment where the bit "1" is coded as "1-" (25% duty cycle) or "1+" (75% duty cycle) based on the running DC value (’044 Patent, col. 3:29-41, Fig. 2A). A party may argue this limits the term to an explicit, selectable signal state rather than an inherent property of an encoding scheme.

For the ’092 Patent:

  • The Term: "modulating a falling edge" (Claim 1)
  • Context and Importance: The claim is specific to modulating the falling edge to encode data, while the specification emphasizes that this "preserves the rising edge of the clock for clock recovery" (’092 Patent, col. 4:34-36). The complaint alleges the accused device uses PWM, a form of clock-edge modulation. Infringement will depend on whether this general modulation scheme can be proven to meet the specific claim requirement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The Abstract broadly describes a clock signal with a "variable position falling edge." A party could argue that any PWM scheme where the falling edge's position changes relative to the rising edge meets this limitation, regardless of other signal characteristics.
    • Evidence for a Narrower Interpretation: The emphasis on preserving the rising edge for clock recovery (’092 Patent, col. 4:34-36) could be used to argue that the term requires a stable, periodic rising edge as a reference point. This might exclude modulation schemes where both edges are subject to variation or jitter.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement, asserting that HPI had knowledge of infringement at least from the filing date of the complaint. It claims HPI took affirmative steps to encourage infringement by "creating advertisements," "creating established distribution channels," and "distributing or making available instructions or manuals" for the accused products (Compl. ¶¶21, 36, 51).
  • Willful Infringement: The willfulness allegation is based on HPI's alleged knowledge of infringement "at least as early as the service date of this Original Complaint" (Compl. ¶¶20, 35, 50). No facts suggesting pre-suit knowledge are alleged.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A key evidentiary question will be one of technical specificity: Does the complaint's reliance on high-level descriptions of the UFS and M-PHY standards provide sufficient factual support to demonstrate that the accused products practice the specific technical limitations of the claims—namely, the use of PWM to incorporate DC-balancing control signals (’044 patent), the specific modulation of the falling edge (’092 patent), and the deliberate shifting of the energy spectrum of an encoded data signal (’593 patent)?
  • A central legal issue will be one of claim construction: Can the functions inherent in the accused M-PHY industry standard be mapped onto the specific claim language? The case will likely hinge on whether the court adopts a broad construction that reads on the standard's general operation or a narrow construction, based on specific embodiments in the patents, that distinguishes the claimed inventions from the accused functionality.