DCT

1:19-cv-00305

Innovative Foundry Tech LLC v. BBK Communication Technology Co Ltd

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-00305, D. Del., 02/13/2019
  • Venue Allegations: Venue is alleged to be proper because the Defendants are not residents of the United States and may therefore be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendants’ smartphones, tablets, and other electronic devices contain semiconductor components that are either manufactured by processes or possess structures that infringe five U.S. patents.
  • Technical Context: The technology at issue relates to fundamental methods and structures for fabricating advanced semiconductor integrated circuits, such as those used in processors and other key components of modern consumer electronics.
  • Key Procedural History: The asserted patents are described as stemming from research and design by Advanced Micro Devices, Inc. (AMD). The complaint alleges that Plaintiff provided Defendants with actual notice of the asserted patents via a letter dated February 8, 2019, five days prior to the filing of the complaint.

Case Timeline

Date Event
2001-02-13 Priority Date for U.S. Patent No. 6,583,012
2003-06-24 U.S. Patent No. 6,583,012 Issued
2003-07-11 Priority Date for U.S. Patent No. 6,797,572
2004-07-12 Priority Date for U.S. Patent No. 7,009,226
2004-09-29 U.S. Patent No. 6,797,572 Issued
2006-03-07 U.S. Patent No. 7,009,226 Issued
2006-09-18 Priority Date for U.S. Patent No. 9,373,548
2008-07-28 Priority Date for U.S. Patent No. 7,880,236
2011-02-01 U.S. Patent No. 7,880,236 Issued
2016-06-21 U.S. Patent No. 9,373,548 Issued
2019-02-08 Plaintiff sends notice letter to Defendant BBK
2019-02-13 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,583,012 - “Semiconductor Devices Utilizing Differently Composed Metal-Based In-Laid Gate Electrodes”, Issued June 24, 2003

The Invention Explained

  • Problem Addressed: The patent describes the limitations of using traditional polysilicon for transistor gate electrodes as device dimensions shrink, including higher electrical resistance and incompatibility with newer "high-k" gate dielectric materials. It also highlights the difficulty in using different metals to optimize performance for different transistor types (e.g., NMOS and PMOS) within the same integrated circuit (Compl. ¶18; ’012 Patent, col. 1:44–col. 2:51).
  • The Patented Solution: The patent discloses a method to form "in-laid" (or damascene) metal gate electrodes with different compositions on a single chip. The process involves depositing a first metal layer, selectively masking some transistor regions, depositing a second material (a different metal or silicon), and then using a reaction like alloying or silicidation to create a second, distinct gate material in the unmasked regions, allowing for tailored performance characteristics for different transistors (’012 Patent, Abstract; col. 5:54–col. 6:6).
  • Technical Importance: This methodology provided a pathway to integrate different, optimized metal gate electrodes for both NMOS and PMOS transistors within a single CMOS device, a key step in moving beyond polysilicon to achieve higher transistor performance (’012 Patent, col. 5:20–34).

Key Claims at a Glance

  • The complaint asserts claims 1-11 of the ’012 Patent (Compl. ¶30).
  • Independent Claim 1 is a method claim with the following essential elements:
    • Providing a semiconductor substrate;
    • Forming at least first and second spaced-apart active device precursor regions;
    • Forming a first metal-based, in-laid gate electrode comprised of a first metal in contact with the first active device precursor region; and
    • Forming a second metal-based, in-laid gate electrode in contact with the second active device precursor region, where the second electrode is comprised of an alloy of the first metal with a second metal/semi-metal or a silicide of the first metal.

U.S. Patent No. 6,797,572 - “Method For Forming a Field Effect Transistor Having a High-K Gate Dielectric and Related Structure”, Issued September 29, 2004

The Invention Explained

  • Problem Addressed: The patent explains that when using high-k gate dielectrics in transistors, a low-quality "interfacial oxide layer" often forms between the silicon substrate and the high-k material. This unwanted layer can grow uncontrollably during fabrication, increasing the effective thickness of the gate dielectric and degrading device performance. Additionally, elements from the high-k material can diffuse into the silicon channel, harming carrier mobility (’572 Patent, col. 1:36–51).
  • The Patented Solution: The invention describes a method to control this interface. First, a thin, high-quality interfacial oxide layer is formed. Next, an "oxygen-attracting layer" is deposited on top of it. This layer, made of a metal like zirconium or hafnium, scavenges excess oxygen from the environment and from the subsequently deposited high-k dielectric, which "prevents the first thickness of the interfacial oxide layer from increasing" (’572 Patent, Abstract; col. 2:8–16).
  • Technical Importance: This technique enables the use of high-k materials to create thinner effective gate dielectrics while preventing the degradation of the critical interface between the silicon channel and the dielectric, which is essential for reliable, high-performance transistors (’572 Patent, col. 3:36–48).

Key Claims at a Glance

  • The complaint asserts claims 1-7 of the ’572 Patent (Compl. ¶46).
  • Independent Claim 1 is a method claim with the following essential elements:
    • Forming an interfacial oxide layer over a channel region, the layer having a first thickness;
    • Forming an oxygen-attracting layer over the interfacial oxide layer;
    • Forming a high-k dielectric layer over the oxygen-attracting layer;
    • Forming a gate electrode layer over the high-k dielectric layer;
    • Wherein the oxygen-attracting layer prevents the first thickness of the interfacial oxide layer from increasing.

U.S. Patent No. 7,009,226 - “In-Situ Nitride/Oxynitride Processing With Reduced Deposition Surface Pattern Sensitivity”, Issued March 7, 2006

  • Technology Synopsis: This patent addresses the problem where dielectric layers used to insulate transistors deposit unevenly depending on the density of the underlying circuit patterns (’226 Patent, col. 2:20-29). The invention discloses a device structure that includes a "stressed nitride liner" over the transistors and a thin, conformal "silicon oxynitride layer" on top of the liner, which together serve to buffer against this pattern sensitivity and allow for a more uniform deposition of the final insulating dielectric layer (’226 Patent, Abstract).
  • Asserted Claims: Claims 1-9 are asserted (Compl. ¶62). Independent Claim 1 is a device claim.
  • Accused Features: The complaint accuses the semiconductor devices within Defendants' products of having the infringing structure, including the specified arrangement of the substrate, transistors, stressed nitride liner, and dielectric layer (Compl. ¶61, 63).

U.S. Patent No. 7,880,236 - “Semiconductor Circuit Including a Long Channel Device and a Short Channel Device”, Issued February 1, 2011

  • Technology Synopsis: This patent addresses threshold voltage instability in "long channel" transistors, which is caused by non-uniform distribution of oxygen vacancies in high-k gate dielectrics (’236 Patent, col. 5:35-46). The patented solution is a device structure where a long channel transistor is constructed from a series of shorter, minimum-length gate segments that are electrically connected. This segmented design allows for more uniform lateral oxygen diffusion during manufacturing, resulting in a more stable long channel device (’236 Patent, Abstract).
  • Asserted Claims: Claims 1-18 are asserted (Compl. ¶78). Independent Claim 1 is a circuit claim.
  • Accused Features: The complaint accuses semiconductor circuits in Defendants' products that contain the specific structure of a long channel device composed of a plurality of electrically coupled first gate electrodes adjacent to a short channel device (Compl. ¶77, 79).

U.S. Patent No. 9,373,548 - “CMOS Circuit Having a Tensile Stress Layer Overlying an NMOS Transistor and Overlapping a Portion of Compressive Stress Layer”, Issued June 21, 2016

  • Technology Synopsis: This patent seeks to optimize transistor performance by using mechanical stress, where a tensile stress liner improves NMOS transistor performance and a compressive stress liner improves PMOS transistor performance (’548 Patent, col. 1:40-53). The invention is a specific CMOS circuit structure where the tensile stress liner over the NMOS device overlaps with the compressive stress liner over the PMOS device in the isolation region between them. This stacked overlap is purported to create an enhanced transverse stress that further boosts performance (’548 Patent, Abstract).
  • Asserted Claims: Claims 1-3 are asserted (Compl. ¶94). Independent Claim 1 is a circuit claim.
  • Accused Features: The complaint accuses CMOS circuits within Defendants' products of having the specific claimed arrangement of tensile and compressive stress liners in a stacked configuration over adjacent NMOS and PMOS transistors (Compl. ¶93, 95).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the Accused Products as a broad category of electronics sold under the BBK corporate umbrella, including but not limited to smartphones, tablets, televisions, and smartwatches from the Oppo, Vivo, and OnePlus brands. The allegations target products containing semiconductor devices manufactured at 5-65 nanometer technology nodes (Compl. ¶25).

Functionality and Market Context

  • The complaint alleges these products incorporate semiconductor devices and integrated circuits that provide their core functionality (Compl. ¶25, 35). The infringement allegations are not directed at the end-user functionality of the smartphones themselves, but at the underlying physical structures and manufacturing processes of the semiconductor chips contained within them (Compl. ¶29, 45). The complaint notes that these products are made, used, sold, and imported throughout the United States (Compl. ¶¶2–5). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits (Exhibits F-O) that purportedly detail the infringement of each asserted patent by exemplary products (e.g., Compl. ¶31, 47). In the absence of these exhibits, the infringement analysis is based on the narrative allegations in the complaint.

  • '012 Patent Infringement Allegations

    • Summary of Allegations: Plaintiff alleges that the semiconductor chips within the Accused Products are manufactured using processes that meet the limitations of the method claims of the ’012 Patent, including claim 1 (Compl. ¶30). The core of this allegation is that the manufacturing process involves forming distinct in-laid metal gate electrodes for different transistors, where one electrode's composition is an alloy or silicide derived from the metal of another, as described in the patent (Compl. ¶31).
    • Identified Points of Contention: A primary issue will be evidentiary. Plaintiff must prove, likely through extensive reverse engineering and discovery from the chip foundry, the specific sequence of steps and materials used in the manufacturing process. A potential point of dispute may be whether the process used for the accused chips forms the second gate electrode through the specific "alloying or silicidation reaction" required by the claim, or through a different deposition method.

  • '572 Patent Infringement Allegations

    • Summary of Allegations: Plaintiff alleges that the manufacturing processes used for the chips in the Accused Products infringe the method claims of the ’572 Patent (Compl. ¶46). The narrative theory is that the process for forming the transistor gate stacks involves the sequential formation of an interfacial oxide layer, followed by an "oxygen-attracting layer," and then a high-k dielectric layer, with the specific function of the intermediate layer being to prevent the growth of the initial oxide layer (Compl. ¶47).
    • Identified Points of Contention: The central technical question will be whether a layer in the accused devices' gate stacks functions as an "oxygen-attracting layer" as claimed. The dispute may turn on whether the layer merely acts as a passive diffusion barrier or if it actively scavenges oxygen to perform the claimed function of preventing the underlying interfacial oxide layer from increasing in thickness.

V. Key Claim Terms for Construction

  • For the ’012 Patent:

    • The Term: "in-laid gate electrode"
    • Context and Importance: This term, synonymous with a "damascene" gate, is fundamental to the claimed manufacturing method. Its construction will define the scope of processes that can be found to infringe. Practitioners may focus on this term because proof of infringement requires showing a specific "fill-after-patterning" process, rather than the more traditional "pattern-after-deposition" process.
    • Intrinsic Evidence for a Broader Interpretation: The specification describes the concept generally, and a party could argue that the term should broadly cover any process where a gate electrode is formed by filling a trench previously etched into an insulating layer (’012 Patent, col. 2:25–31).
    • Intrinsic Evidence for a Narrower Interpretation: A party could argue the term is limited by the specific process flows shown in the patent's figures and detailed description, for example requiring the use of a "dummy" gate that is later replaced (’012 Patent, col. 5:65–col. 6:4) or specific self-aligned silicide steps (’012 Patent, col. 3:55–col. 4:16).

  • For the ’572 Patent:

    • The Term: "oxygen-attracting layer"
    • Context and Importance: This term captures the core of the asserted invention in claim 1. The outcome of the infringement analysis depends heavily on whether any layer in the accused devices' gate stack meets this functional and compositional definition.
    • Intrinsic Evidence for a Broader Interpretation: The patent describes the layer as one formed by depositing a metal (like hafnium or zirconium) that "attracts and combines with excessive oxygen" (’572 Patent, col. 4:12–16). A party may argue that any layer containing such a metal, which is known to oxidize, meets the definition.
    • Intrinsic Evidence for a Narrower Interpretation: The claim includes the functional limitation that the layer "prevents said first thickness of said interfacial oxide layer from increasing." A party may argue that this requires proof not just of the layer’s composition, but of its actual effect during the manufacturing process. The patent also describes the resulting layer as a "silicate" (’572 Patent, col. 2:14-16), which could be used to argue for a narrower definition limited to a specific final composition.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced and contributory infringement for all asserted patents. Inducement is primarily based on allegations that Defendants knew of the patents and intended for others (e.g., customers, resellers) to sell and import the accused products, which were manufactured using infringing processes or have infringing structures (Compl. ¶32-33, 48-49). The claim for contributory infringement is based on the allegation that the accused semiconductor devices are a material part of the invention and have no substantial non-infringing uses (Compl. ¶35, 51).
  • Willful Infringement: For each asserted patent, the complaint alleges willful infringement. The basis for willfulness is alleged pre-suit knowledge stemming from a notice letter dated February 8, 2019, as well as continued infringement after the complaint was filed (Compl. ¶36, 40-41, 52, 56-57).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central challenge for the plaintiff will be one of evidentiary proof: for the method patents ('012, '572), can the plaintiff demonstrate through reverse engineering and discovery that the specific, multi-step manufacturing processes recited in the claims were actually used to create the semiconductor chips inside the numerous accused products?
  • A key claim construction issue will be one of functional definition: for the '572 patent, does a layer in the accused devices’ gate stacks perform the specific claimed function of an "oxygen-attracting layer" that "prevents said first thickness of said interfacial oxide layer from increasing," or is it a structurally similar but functionally distinct layer, such as a simple diffusion barrier?
  • For the patents claiming specific device structures ('226, '236, '548), a core infringement question will be one of structural correspondence: do the physical layouts of stress liners, segmented gate electrodes, and insulating layers in the accused chips map directly onto the specific arrangements, overlaps, and electrical connections required by the claims, or are there material differences in their physical architecture?