DCT

1:19-cv-00307

Innovative Foundry Tech LLC v. TCL Corp

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-00307, D. Del., 02/13/2019
  • Venue Allegations: Venue is asserted against foreign defendant TCL Corporation under 28 U.S.C. § 1391(c)(3) and against its U.S. subsidiaries under 28 U.S.C. § 1400(b), alleging they reside in and have committed acts of infringement in the District of Delaware.
  • Core Dispute: Plaintiff alleges that Defendants’ consumer electronics, which incorporate semiconductor devices manufactured at advanced technology nodes, infringe five patents related to semiconductor fabrication methods and device structures.
  • Technical Context: The patents-in-suit relate to fundamental techniques in advanced semiconductor manufacturing designed to improve transistor performance, such as creating tailored metal gates, managing high-k dielectric layers, and using stress to enhance carrier mobility.
  • Key Procedural History: The complaint alleges the asserted patents originate from research by Advanced Micro Devices, Inc. (AMD), which has licensed the patents to the Plaintiff. Plaintiff alleges to have placed Defendants on actual notice of the asserted patents via a letter dated February 8, 2019, five days prior to filing the complaint.

Case Timeline

Date Event
2001-02-13 U.S. Patent No. 6,583,012 Priority Date (Filing Date)
2003-06-24 U.S. Patent No. 6,583,012 Issued
2003-07-11 U.S. Patent No. 6,797,572 Priority Date (Filing Date)
2004-07-12 U.S. Patent No. 7,009,226 Priority Date (Filing Date)
2004-09-29 U.S. Patent No. 6,797,572 Issued
2006-03-07 U.S. Patent No. 7,009,226 Issued
2006-09-18 U.S. Patent No. 9,373,548 Earliest Priority Date
2008-07-28 U.S. Patent No. 7,880,236 Priority Date (Filing Date)
2011-02-01 U.S. Patent No. 7,880,236 Issued
2016-06-21 U.S. Patent No. 9,373,548 Issued
2019-02-08 Plaintiff sent letter providing actual notice of patents
2019-02-13 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,583,012 - “Semiconductor Devices Utilizing Differently Composed Metal-Based In-Laid Gate Electrodes,” issued June 24, 2003

The Invention Explained

  • Problem Addressed: The patent describes the challenges in advanced CMOS manufacturing, where different types of transistors (e.g., NMOS and PMOS) ideally require gate electrodes made from different metals to optimize their performance. However, fabricating different metal gates for different transistors using conventional methods is complex, often requiring separate, difficult etching and patterning steps for each metal (’012 Patent, col. 6:20-44).
  • The Patented Solution: The invention proposes a damascene (in-laid) process to form two different gate electrode compositions with a single planarization step. The method involves depositing a first blanket metal layer, masking the areas for one type of transistor, and then depositing a second metal or silicon layer. An alloying or silicidation reaction is then induced between the first and second layers in the unmasked areas, creating a second gate material with different properties from the first. The structure is then planarized, leaving two distinct, in-laid gate electrodes (’012 Patent, Abstract; col. 7:15-8:4, Figs. 17-22).
  • Technical Importance: This methodology provides a way to integrate different metal-based gate materials needed for high-performance CMOS devices in a more efficient and manufacturable way, avoiding the complexities of patterning and etching multiple, disparate metals (’012 Patent, col. 6:45-53).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2-11 (Compl. ¶30).
  • Independent claim 1 is a method claim with the following essential elements:
    • Providing a semiconductor substrate.
    • Forming at least first and second spaced-apart, active device precursor regions.
    • Forming a first metal-based, in-laid gate electrode comprised of a first metal in contact with the first active device precursor region.
    • Forming a second metal-based, in-laid gate electrode in contact with the second active device precursor region, where the second electrode is comprised of an alloy of the first metal with a second metal or semi-metal, or of an electrically conductive silicide of the first metal.

U.S. Patent No. 6,797,572 - “Method For Forming a Field Effect Transistor Having a High-K Gate Dielectric and Related Structure,” issued September 29, 2004

The Invention Explained

  • Problem Addressed: The patent notes that when using high-dielectric constant (high-k) materials for a gate insulator, conventional fabrication processes can create a poor-quality interfacial oxide layer between the high-k material and the silicon substrate. This unwanted layer increases the effective thickness of the gate dielectric and can degrade transistor performance and reliability (’572 Patent, col. 1:31-55).
  • The Patented Solution: The invention discloses a method to better control the gate dielectric stack. The key steps involve first forming a very thin, high-quality interfacial oxide layer on the substrate, then depositing an "oxygen-attracting layer" (e.g., a metal like hafnium or zirconium), and finally depositing the bulk high-k dielectric layer. The oxygen-attracting layer reacts with and scavenges excess oxygen, preventing the underlying high-quality interfacial layer from growing thicker during subsequent high-temperature processing steps (’572 Patent, Abstract; col. 2:7-24; Fig. 2).
  • Technical Importance: This technique enables the fabrication of transistors with stable, ultra-thin high-k gate dielectrics, which is critical for minimizing current leakage in scaled-down devices without sacrificing performance due to unwanted oxide growth or degraded carrier mobility (’572 Patent, col. 4:36-52).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2-7 (Compl. ¶46).
  • Independent claim 1 is a method claim with the following essential elements:
    • Forming an interfacial oxide layer over a channel region, the layer having a first thickness.
    • Forming an oxygen-attracting layer over the interfacial oxide layer.
    • Forming a high-k dielectric layer over the oxygen-attracting layer.
    • Forming a gate electrode layer over the high-k dielectric layer.
    • The claim includes the functional limitation that the oxygen-attracting layer "prevents said first thickness of said interfacial oxide layer from increasing."

U.S. Patent No. 7,009,226 - “In-Situ Nitride/Oxynitride Processing With Reduced Deposition Surface Pattern Sensitivity,” issued March 7, 2006

Technology Synopsis

The patent addresses non-uniformity in the deposition of dielectric gap-fill layers, a problem exacerbated by the topography of underlying transistors (’226 Patent, col. 2:17-28). The proposed solution involves applying a stressed nitride liner over the transistors, then treating its surface to form a thin, conformal silicon oxynitride layer, which serves as a buffer to enable a more uniform deposition of the subsequent dielectric material (’226 Patent, Abstract).

Asserted Claims

Claims 1-9 are asserted, with claim 1 being independent (Compl. ¶62).

Accused Features

The complaint accuses the semiconductor devices within the Blackberry DTEK50 smartphone of infringing (Compl. ¶63).

U.S. Patent No. 7,880,236 - “Semiconductor Circuit Including a Long Channel Device and a Short Channel Device,” issued February 1, 2011

Technology Synopsis

The patent addresses the difficulty of optimizing long-channel transistors (often used in analog circuits) with the same high-k/metal gate processes that work well for short-channel digital transistors (’236 Patent, col. 5:1-24). The invention describes a long-channel device constructed from a series of electrically-connected, minimum-length gate segments. This structure allows fabrication techniques optimized for short channels to be effectively applied to a device that behaves electrically as a long-channel transistor (’236 Patent, Abstract; col. 6:25-50).

Asserted Claims

Claims 1-18 are asserted, with claims 1, 13, and 17 being independent (Compl. ¶78).

Accused Features

The complaint accuses semiconductor circuits within the Alcatel A50 smartphone and TCL 55R617 television of infringing (Compl. ¶79).

U.S. Patent No. 9,373,548 - “CMOS Circuit Having a Tensile Stress Layer Overlying an NMOS Transistor and Overlapping a Portion of Compressive Stress Layer,” issued June 21, 2016

Technology Synopsis

The patent describes a method for integrating tensile and compressive stress liners, used to boost performance in NMOS and PMOS transistors, respectively. To mitigate the negative interactions where the liners meet, the invention specifies a particular stacked geometry where the tensile stress liner partially overlaps the edge of the compressive stress liner. This defined overlap is intended to generate an enhanced transverse stress, improving device performance beyond what either liner could achieve alone (’548 Patent, Abstract).

Asserted Claims

Claims 1-3 are asserted, with claim 1 being independent (Compl. ¶94).

Accused Features

The complaint accuses the CMOS circuits within the Blackberry DTEK50 smartphone of infringing (Compl. ¶95).

III. The Accused Instrumentality

Product Identification

The complaint identifies the Accused Products as a broad category of "all TCL smartphones, tablets, televisions, smartwatches, and products that include semiconductor devices and integrated circuits manufactured at 5-65 nanometer technology nodes" (Compl. ¶25). Dozens of specific models are listed as non-limiting examples, including the Alcatel, Blackberry, and TCL-branded product lines (Compl. ¶25).

Functionality and Market Context

The complaint does not focus on the end-user functionality of the accused consumer electronics. Instead, it alleges that the vital functionality of these devices is enabled by internal semiconductor components (Compl. ¶¶35, 51). The infringement allegations are directed at the manufacturing processes and fine-grained physical structures of these internal integrated circuits, which are sourced by Defendants and incorporated into their downstream products (Compl. ¶¶2-5, 19).

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits detailing its infringement theories. The following summarizes the narrative infringement allegations for the lead patents.

'012 Patent Infringement Allegations

The complaint alleges that the processes used to manufacture the semiconductor devices found in products such as the Alcatel A50 smartphone and the TCL 55R617 television infringe at least claim 1 of the '012 Patent (Compl. ¶¶30-31). The core of this allegation is that the manufacturers of these chips employ a method that forms at least two different types of metal-based, in-laid gate electrodes. Specifically, the complaint alleges that one type of gate electrode is formed from a first metal, while a second type is formed from an alloy or silicide created by reacting that first metal with a subsequently deposited material, thereby practicing the patented method (Compl. ¶¶29, 31). No probative visual evidence provided in complaint.

'572 Patent Infringement Allegations

The complaint alleges that the manufacturing processes for semiconductor devices in products including the Alcatel A50 smartphone and TCL 55R617 television infringe at least claim 1 of the '572 Patent (Compl. ¶¶46-47). The infringement theory is that the method for forming the high-k gate dielectric stacks in these devices includes the steps of forming a thin interfacial oxide layer, followed by forming an "oxygen-attracting layer" over it. This layer is alleged to perform the claimed function of preventing the interfacial oxide layer from growing thicker during subsequent processing steps, thereby mapping to the patented method (Compl. ¶¶45, 47). No probative visual evidence provided in complaint.

Identified Points of Contention

  • Evidentiary Questions: For all asserted patents, which claim complex manufacturing methods and specific nanometer-scale structures, the central dispute will likely be evidentiary. A primary question is whether Plaintiff can produce sufficient evidence, through reverse engineering or discovery from Defendants' semiconductor suppliers, to demonstrate that the accused manufacturing processes use the exact sequence of steps and create the precise material compositions and structures required by the claims.
  • Scope Questions ('012 Patent): A key question is whether the accused manufacturing process creates the second gate electrode by alloying or silicidizing the first metal, as required by claim 1. If the process instead uses, for example, two entirely separate deposition and etch steps for two different metals, it may fall outside the claim's scope.
  • Technical & Functional Questions ('572 Patent): The infringement analysis will likely focus on the functional language of claim 1. A point of contention may be whether a layer in the accused process is in fact an "oxygen-attracting layer" and, more specifically, whether it "prevents said first thickness of said interfacial oxide layer from increasing." The defense may question whether any intermediate layer performs this specific preventative function, or if it has a different primary purpose and effect.

V. Key Claim Terms for Construction

'012 Patent, Claim 1

  • The Term: "an alloy of the first metal with a second metal or semi-metal or of an electrically conductive silicide of the first metal"
  • Context and Importance: This phrase defines the composition of the second gate electrode and is the central point of novelty in the claimed method. The infringement analysis for the '012 patent hinges on whether the accused process forms the second gate electrode through this specific in-situ reaction, as opposed to other methods of forming multi-metal gates.
  • Intrinsic Evidence for a Broader Interpretation: The specification provides a wide range of candidate materials for the "second metal or semi-metal," including elements from numerous groups in the periodic table, suggesting the inventive concept is not limited to a narrow set of materials ('012 Patent, col. 8:12-16).
  • Intrinsic Evidence for a Narrower Interpretation: The claim requires the second electrode to be an "alloy" or "silicide" of the first metal. The specification repeatedly describes an "alloying or silicidation reaction" ('012 Patent, col. 8:1-2, 12:23-27). A party might argue this requires an active, in-situ thermal reaction process and would not cover, for example, the deposition of a pre-alloyed material.

'572 Patent, Claim 1

  • The Term: "oxygen-attracting layer"
  • Context and Importance: This term is central to the patent's proposed solution for controlling the thickness of the gate dielectric stack. As the term is defined by its function, its construction will determine what types of material layers in the accused process could be considered infringing. Practitioners may focus on this term because its scope is not explicitly defined by structure alone.
  • Intrinsic Evidence for a Broader Interpretation: The patent abstract and detailed description characterize the layer by its function: it "attracts excessive oxygen" ('572 Patent, col. 3:22-25). Plaintiff may argue that any layer demonstrated to perform this function falls within the claim's scope, regardless of its exact composition.
  • Intrinsic Evidence for a Narrower Interpretation: The specification provides specific examples of how the layer is formed, such as by depositing a metal (e.g., hafnium, zirconium) that "combines with oxygen to form a silicate" ('572 Patent, col. 2:12-16). A defendant may argue that the term should be limited to a layer that begins as a pure metal and is subsequently converted through oxygen absorption, and does not cover, for instance, a pre-fabricated silicate layer deposited directly.

VI. Other Allegations

Indirect Infringement

The complaint alleges Defendants induce infringement by providing instructions and user guides for the accused end-products (e.g., Compl. ¶¶34, 50). It further alleges contributory infringement, asserting that the accused products cannot be used without their internal semiconductor components and therefore have no substantial non-infringing use (e.g., Compl. ¶¶35, 51).

Willful Infringement

Willfulness is alleged for all five asserted patents. The basis for these allegations is Defendants' alleged continued infringement after receiving a letter dated February 8, 2019, which provided actual notice of the asserted patents (e.g., Compl. ¶¶41, 57, 68, 84, 100).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A primary issue will be one of evidentiary proof for manufacturing processes: Given that the patents claim highly specific semiconductor manufacturing methods and the resulting nanostructures, and Defendants are downstream product integrators, can Plaintiff obtain direct evidence from third-party foundries to prove that the accused chips are in fact made using processes that meet the specific, multi-step limitations of the asserted claims?
  • A second core issue will be one of functional claim scope: Will the term "oxygen-attracting layer" in the '572 patent be construed broadly to cover any layer that has the effect of limiting oxide growth, or will it be limited to the specific embodiment of a pure metal layer that actively scavenges oxygen to form a silicate, potentially creating a non-infringement defense?
  • A third question will concern infringement under 35 U.S.C. § 271(g): For the asserted method claims, the case will depend on Plaintiff's ability to prove that the semiconductor components within Defendants' products sold in the U.S. were manufactured abroad using the patented processes. This will require tracing the supply chain and analyzing the specific techniques employed by the overseas foundries that supply TCL.