DCT

1:19-cv-00308

Innovative Foundry Tech LLC v. Taiwan Semiconductor Mfg Co Ltd

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-00308, D. Del., 02/13/2019
  • Venue Allegations: Venue is asserted on the basis that Defendant TSMC Technology, Inc. is a Delaware corporation residing in the district, and Defendant Taiwan Semiconductor Manufacturing Company Limited is a foreign entity that may be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices and integrated circuits, manufactured using a wide range of advanced process nodes, infringe five U.S. patents concerning semiconductor fabrication methods, transistor structures, and stress engineering.
  • Technical Context: The technology concerns fundamental processes for manufacturing advanced transistors, the core components of modern integrated circuits, with a focus on integrating new materials (high-k dielectrics, metal gates) and mechanical stress techniques to improve performance.
  • Key Procedural History: The asserted patents are said to originate from research by Advanced Micro Devices, Inc. (AMD). The complaint alleges that Plaintiff provided Defendants with actual notice of the asserted patents via a letter dated February 8, 2019, five days prior to filing the suit.

Case Timeline

Date Event
2001-02-13 U.S. Patent No. 6,583,012 Priority Date
2003-06-24 U.S. Patent No. 6,583,012 Issue Date
2003-07-11 U.S. Patent No. 6,797,572 Priority Date
2004-07-12 U.S. Patent No. 7,009,226 Priority Date
2004-09-29 U.S. Patent No. 6,797,572 Issue Date
2006-03-07 U.S. Patent No. 7,009,226 Issue Date
2006-09-18 U.S. Patent No. 9,373,548 Priority Date
2008-07-28 U.S. Patent No. 7,880,236 Priority Date
2011-02-01 U.S. Patent No. 7,880,236 Issue Date
2016-06-21 U.S. Patent No. 9,373,548 Issue Date
2019-02-08 Plaintiff sends notice letter to TSMC
2019-02-13 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,583,012 - "Semiconductor Devices Utilizing Differently Composed Metal-Based In-Laid Gate Electrodes"

The Invention Explained

  • Problem Addressed: The patent describes the limitations of conventional polysilicon gate electrodes in advanced transistors, such as high electrical resistance and "poly depletion" effects that degrade performance, particularly as design rules shrink below 0.20 µm (’012 Patent, col. 1:59-2:5). While metal gates are a solution, fabricating devices that require different metal gates for different transistor types (e.g., NMOS and PMOS) on the same wafer is complex and can damage sensitive underlying layers (’012 Patent, col. 2:55-68).
  • The Patented Solution: The patent discloses a method to form multiple, differently composed metal gates using a damascene, or "in-laid," process. The method involves blanket-depositing a first metal layer into pre-formed openings, selectively masking some regions, depositing a second material (a metal or silicon), and then using a thermal process to cause an alloying or silicidation reaction only in the unmasked areas (’012 Patent, Abstract; col. 6:53-col. 7:4). As illustrated in Figures 17-22, this allows for the creation of a first gate made of a pure metal and a second gate made of an alloy or silicide, tailoring the electronic properties for different transistors without multiple complex etch steps (’012 Patent, Figs. 17-22).
  • Technical Importance: This methodology provided a pathway for integrating different metal gate materials required for high-performance CMOS devices, enabling the optimization of both NMOS and PMOS transistors on a single chip (’012 Patent, col. 6:11-25).

Key Claims at a Glance

  • The complaint asserts claims 1-11 (Compl. ¶29). Independent claim 1 is a method claim.
  • Essential elements of claim 1 include:
    • Providing a semiconductor substrate and forming at least first and second active device precursor regions.
    • Forming a first metal-based, in-laid gate electrode comprised of a first metal in the first region.
    • Forming a second metal-based, in-laid gate electrode in the second region, where this second electrode is comprised of either an alloy of the first metal with a second metal/semi-metal, or a silicide of the first metal.
  • The complaint alleges infringement of one or more claims, reserving the right to assert others, including dependent claims (Compl. ¶28).

U.S. Patent No. 6,797,572 - "Method For Forming a Field Effect Transistor Having a High-K Gate Dielectric and Related Structure"

The Invention Explained

  • Problem Addressed: The patent explains that when fabricating transistors with high-k gate dielectrics, excessive oxygen from the high-k material can react with the silicon substrate to form an undesirable, "low-quality interfacial oxide layer." This unintended layer increases the effective thickness of the gate dielectric, harming device performance, and can allow high-k elements to diffuse into the silicon channel, degrading carrier mobility (’572 Patent, col. 1:36-51).
  • The Patented Solution: The invention proposes a multi-layer gate stack to solve this problem. First, a thin, high-quality interfacial oxide layer is intentionally formed on the substrate. Next, an "oxygen-attracting layer" (e.g., a metal like zirconium or hafnium) is deposited. Finally, the main high-k dielectric is deposited. This intermediate oxygen-attracting layer getters, or absorbs, excess oxygen from the high-k material, reacting with it to form a silicate and preventing the initial, high-quality interfacial layer from growing thicker (’572 Patent, Abstract; col. 2:7-24). The complete structure is shown in the patent's Figure 4, which details the stack of interfacial oxide, oxygen-attracting layer, and high-k dielectric (’572 Patent, Fig. 4).
  • Technical Importance: This method provides a technique to control the critical interface between the silicon channel and the high-k gate dielectric, which is essential for realizing the performance benefits of high-k materials while maintaining device reliability (’572 Patent, col. 4:35-42).

Key Claims at a Glance

  • The complaint asserts claims 1-7 (Compl. ¶45). Independent claim 1 is a method claim.
  • Essential elements of claim 1 include:
    • Forming an interfacial oxide layer of a "first thickness" over a channel region.
    • Forming an "oxygen-attracting layer" over the interfacial oxide layer.
    • Forming a high-k dielectric layer over the oxygen-attracting layer.
    • Forming a gate electrode layer.
    • A functional limitation: "wherein said oxygen-attracting layer prevents said first thickness of said interfacial oxide layer from increasing."
  • The complaint alleges infringement of one or more claims, reserving the right to assert others (Compl. ¶44).

U.S. Patent No. 7,009,226 - "In-Situ Nitride/Oxynitride Processing With Reduced Deposition Surface Pattern Sensitivity"

  • Technology Synopsis: The patent addresses "deposition surface pattern sensitivity," where a dielectric layer deposits at different thicknesses on dense versus isolated regions of a chip (’226 Patent, col. 2:20-27). The solution is a device structure that includes a stressed nitride liner (for performance enhancement) and a conformal silicon oxynitride layer formed on top of the liner. This oxynitride layer acts as a transitional surface that reduces pattern sensitivity during the subsequent gap-filling dielectric deposition, resulting in a more uniform final structure (’226 Patent, Abstract; col. 4:5-16).
  • Asserted Claims: Claims 1-9 are asserted (Compl. ¶61).
  • Accused Features: The complaint accuses TSMC's 28 nm LP technology node of infringing, targeting the structure of transistors that use stressed liners and interlayer dielectrics (Compl. ¶62, ¶64).

U.S. Patent No. 7,880,236 - "Semiconductor Circuit Including a Long Channel Device and a Short Channel Device"

  • Technology Synopsis: The patent addresses a problem in high-k/metal gate devices where the threshold voltage can vary with channel length due to non-uniform oxygen vacancy distribution, an issue particularly acute in "long channel" transistors used in analog circuits (’236 Patent, col. 5:1-9). The invention proposes fabricating a long channel device not with one continuous gate, but with a series of electrically connected, minimum-length gate segments. This structure allows for more uniform lateral diffusion of oxygen under each short segment, stabilizing the threshold voltage across the entire effective long channel device (’236 Patent, Abstract; col. 6:35-44).
  • Asserted Claims: Claims 1-18 are asserted (Compl. ¶77).
  • Accused Features: The complaint accuses TSMC’s 16 nm FinFET and 28 nm HKMG technologies, alleging their long and short channel device structures infringe the patent (Compl. ¶78, ¶80).

U.S. Patent No. 9,373,548 - "CMOS Circuit Having a Tensile Stress Layer Overlying an NMOS Transistor and Overlapping a Portion of Compressive Stress Layer"

  • Technology Synopsis: The patent relates to stress engineering in closely packed CMOS circuits, where the tensile stress liner beneficial for NMOS transistors can interfere with the compressive stress liner beneficial for PMOS transistors (’548 Patent, col. 1:49-58). The invention claims a specific circuit structure where the tensile liner and compressive liner are arranged in a "stacked configuration" over the isolation region separating the NMOS and PMOS devices. This specific overlap is designed to enhance transverse stress and maximize mobility gains for both transistor types simultaneously (’548 Patent, Abstract; col. 2:9-14).
  • Asserted Claims: Claims 1-3 are asserted (Compl. ¶93).
  • Accused Features: The complaint accuses TSMC’s 28 nm LP technology, targeting the physical layout and structure of the dual stress liners used in its CMOS circuits (Compl. ¶94, ¶96).

III. The Accused Instrumentality

  • Product Identification: The complaint broadly accuses semiconductor devices, integrated circuits, and products manufactured using TSMC’s 5-65 nanometer technology nodes (Compl. ¶24). Specific examples cited include the 65 nm, 40 nm, 28 nm, 22 nm, 20 nm, 16 nm, 12 nm, 10 nm, 7 nm, and 5 nm nodes, covering both planar and FinFET architectures (Compl. ¶24).
  • Functionality and Market Context: The accused instrumentalities are not consumer end-products but are the foundational manufacturing processes and the resulting integrated circuits sold by TSMC, a semiconductor foundry. The complaint alleges these circuits are incorporated into a wide variety of downstream electronic products, including smartphones and televisions from companies such as MediaTek, Qualcomm, TCL, and VIZIO (Compl. ¶31-32, ¶47). The accused process nodes represent the core of modern semiconductor manufacturing and are commercially critical to the global electronics industry.

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint. The complaint incorporates by reference Exhibits F through M, which it describes as claim charts detailing the infringement allegations for each patent against exemplary TSMC technology nodes (e.g., Compl. ¶30, ¶46). As these exhibits were not filed with the complaint, the following analysis is based on the narrative infringement theories presented in the complaint's text.

’012 Patent Infringement Allegations

  • Narrative Summary: The complaint alleges that TSMC’s manufacturing processes for its 16 nm FinFET and 28 nm HKMG technology nodes infringe at least claim 1 of the ’012 Patent (Compl. ¶30). The theory of infringement is that TSMC’s processes for forming metal gates for different types of transistors constitute the method claimed in the patent. The complaint relies on unprovided Exhibits F and G to detail these allegations (Compl. ¶30).
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether TSMC's modern "replacement metal gate" (RMG) or "gate-last" processes fall within the scope of the term "in-laid gate electrode" as used in the patent. The court may need to determine if this term is limited to the specific damascene alloying/silicidation process disclosed in the patent's embodiments or if it can be read more broadly to cover other methods of filling a trench with a conductor.
    • Technical Questions: What is the precise composition of the different gate metals used by TSMC? The infringement analysis will depend on whether TSMC’s process creates a second gate electrode that is an "alloy" or "silicide" of a first deposited metal, as strictly required by claim 1.

’572 Patent Infringement Allegations

  • Narrative Summary: The complaint alleges that TSMC’s processes for its 16 nm FinFET and 28 nm HKMG nodes infringe at least claim 1 of the ’572 Patent by using a gate stack that includes an interfacial oxide layer, an oxygen-attracting layer, and a high-k dielectric layer (Compl. ¶46). This theory is allegedly detailed in unprovided Exhibits H and I (Compl. ¶46).
  • Identified Points of Contention:
    • Scope Questions: Does a layer within TSMC's gate stack meet the functional requirements of an "oxygen-attracting layer"? The analysis will raise the question of whether this term requires an active chemical gettering mechanism (as described in the patent) or if it could also read on a passive diffusion barrier that achieves a similar result of preventing interfacial layer growth.
    • Technical Questions: What evidence does the complaint provide that a layer in the accused process "prevents said first thickness of said interfacial oxide layer from increasing"? This is a negative limitation that may require complex material science evidence to prove, focusing on the chemical reactions and stability of the gate stack during fabrication.

V. Key Claim Terms for Construction

For the ’012 Patent

  • The Term: "in-laid gate electrode"
  • Context and Importance: This term is foundational to the claimed method. Its construction will be critical to determining whether the patent's scope covers modern "replacement metal gate" (RMG) processes, which became dominant after the patent was filed. Practitioners may focus on this term because the distinction between the patent's "damascene" disclosure and TSMC's actual RMG process could be case-dispositive.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests the term is synonymous with "damascene" and describes a general process of filling a pre-formed opening, which is conceptually similar to RMG processes (’012 Patent, col. 2:27-29). Plaintiff may argue the term should not be limited to the specific embodiments.
    • Evidence for a Narrower Interpretation: The detailed description and figures illustrate a specific process sequence where source/drain regions are formed via out-diffusion from a silicide before the gate trench is filled (’012 Patent, Figs. 1-7). Defendant may argue the term "in-laid" is inextricably linked to this specific process flow, distinguishing it from modern RMG flows.

For the ’572 Patent

  • The Term: "oxygen-attracting layer"
  • Context and Importance: This term captures the core novelty of the claimed gate stack. The infringement case hinges on whether a layer in TSMC's gate stack performs this precise function. Practitioners may focus on this term because the technical mechanism of the accused layer (active gettering vs. passive barrier) will be a central point of expert dispute.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract and summary state the layer "prevents the first thickness of the interfacial oxide layer from increasing" (’572 Patent, Abstract; col. 2:9-12). Plaintiff may argue that any layer achieving this functional result falls within the claim's scope, regardless of the precise chemical pathway.
    • Evidence for a Narrower Interpretation: The specification explicitly describes the mechanism as a metal layer that "attracts and combines with excessive oxygen... to form a silicate" (’572 Patent, col. 2:12-15). Defendant may argue the term is limited to materials that actively getter oxygen and form a new compound, and would not cover a chemically inert diffusion barrier.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendants induce infringement by designing and selling the accused circuits to downstream customers (e.g., MediaTek, Qualcomm) with the knowledge and intent that those customers will incorporate them into products made, used, or sold in the U.S. (Compl. ¶22, ¶32). The basis for inducement includes the alleged provision of "instructions, user guides, and/or other design documentation" (Compl. ¶33). Contributory infringement is alleged on the grounds that the accused circuits are a material part of the inventions and are not staple articles of commerce with substantial non-infringing uses (Compl. ¶34).
  • Willful Infringement: Willfulness is alleged for all five patents. The claims are based on alleged actual notice provided via a letter to TSMC dated February 8, 2019, and Defendants' alleged continuation of infringing activities after receiving this notice (Compl. ¶19, ¶40, ¶56).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technological scope: can claims drafted and prosecuted in the context of early 2000s planar semiconductor technology be construed to cover modern, structurally distinct 3D FinFET architectures and replacement-metal-gate processes? This raises a fundamental question of whether terms like "in-laid gate electrode" (’012 Patent) or the description of stress liner interactions (’548 Patent) can be mapped onto today's transistor designs.
  • A second central question will be one of functional mechanism: for the ’572 patent, does a layer in TSMC’s gate stack operate as an "oxygen-attracting layer" that actively getters oxygen, as described in the patent, or does it function as a simple, passive diffusion barrier, potentially representing a non-infringing alternative solution to the same technical problem?
  • A key evidentiary question for patents like the '236 and '548 will be one of structural identity: do TSMC's physical circuit layouts for long-channel analog devices or CMOS pairs actually contain the specific structures recited in the claims, such as a long-channel device built from serially-connected short gates (’236 Patent) or the precise overlapping, stacked configuration of stress liners (’548 Patent)?