Altair Logix LLC v. Kontron America Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Kontron America, Incorporated (Delaware)
  • Plaintiff’s Counsel: Devlin Law Firm LLC
• Case Identification: 1:19-cv-00584, D. Del., 03/28/2019
• Venue Allegations: Venue is asserted based on Defendant’s incorporation in Delaware.
• Core Dispute: Plaintiff alleges that Defendant’s SMARC-sAMX6i computer-on-module infringes a patent related to dynamically reconfigurable processor architectures.
• Technical Context: The technology concerns system-on-chip (SoC) architectures with reconfigurable processing units, aiming to achieve the performance of fixed-function hardware with greater flexibility and lower cost.
• Key Procedural History: The complaint alleges that the asserted claim issued without amendment and was not subject to an anticipation rejection during prosecution, a point Plaintiff may leverage to argue for a broad claim scope and rebut potential invalidity challenges.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates

• Patent Identification: U.S. Patent No. 6,289,434, Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates, issued September 11, 2001.

The Invention Explained

• Problem Addressed: The patent describes a tradeoff in chip design between high-performance but inflexible and costly "hard-wired" or "fixed-function" circuits, and more flexible but lower-performing alternatives like general-purpose processors, DSPs, or FPGAs (’434 Patent, col. 1:42-2:33). Fixed-function systems exhibit "temporal redundancy" by dedicating silicon to all possible functions, even when not in use, increasing cost (’434 Patent, col. 2:50-60).
• The Patented Solution: The invention proposes an apparatus with multiple, reconfigurable "media processing units" (MPUs) that can be dynamically reconfigured at run-time. This is achieved by re-using computational and storage elements in different configurations to adapt to varying data and processing needs, which removes redundancy and lowers cost while aiming to maintain high performance (’434 Patent, col. 3:1-11). The architecture is depicted in Figure 3, showing multiple media processing units interconnected on a chip (’434 Patent, Fig. 3).
• Technical Importance: This architecture aimed to merge the high performance of application-specific circuits with the flexibility of programmable devices, addressing a central challenge in system-on-chip design during that era (’434 Patent, col. 2:64-3:1).

Key Claims at a Glance

• The complaint asserts independent claim 1.
• The essential elements of claim 1 include:
  • An addressable memory for storing data and instructions.
  • A plurality of media processing units coupled to the memory.
  • Each media processing unit comprising a multiplier, an arithmetic unit, an arithmetic logic unit, and a bit manipulation unit.
  • The arithmetic logic unit must be capable of operating concurrently with the multiplier and/or the arithmetic unit.
  • The bit manipulation unit must be capable of operating concurrently with the arithmetic logic unit and the multiplier and/or the arithmetic unit.
  • The plurality of media processing units must be capable of performing operations simultaneously with each other.
  • Each operation must comprise receiving an instruction and data from memory, processing the data to produce a result, and providing the result to the media processor input/output.
• The complaint does not explicitly reserve the right to assert dependent claims, as the patent contains only one claim.

III. The Accused Instrumentality

Product Identification

• Product Identification: The Kontron SMARC-sAMX6i, an ARM and SoC-based SMARC (Smart Mobile ARChitecture) module (Compl. ¶26, ¶27).

Functionality and Market Context

• Functionality and Market Context:
  • The Accused Instrumentality is a computer-on-module based on Freescale (NXP) i.MX6 processors, which are available in single, dual, or quad-core configurations using the ARM Cortex-A9 architecture (Compl. ¶27-28, p. 11 screenshot). The complaint identifies the ARM Cortex-A9 cores as the "media processing units," with each core containing a NEON media coprocessor that performs SIMD (Single Instruction, Multiple Data) operations (Compl. ¶28). A block diagram of the i.MX 6Quad processor shows the quad-core ARM platform, including a "NEON per Core" unit, connected to addressable memory and other peripherals (Compl. p. 12, "i.MX 6Quad Multimedia Applications Processor Block Diagram").
  • The product is marketed as a "highly scalable" and "ultra-low power" module for developing "smart devices in an extremely compact, fanless design" (Compl. ¶27, p. 10 screenshot).

IV. Analysis of Infringement Allegations

Claim Chart Summary

Identified Points of Contention

• Scope Questions: The case may turn on whether a standard ARM Cortex-A9 CPU core with its associated NEON SIMD coprocessor falls within the patent's definition of a "media processing unit." The defense may argue that the patent describes a more fundamentally reconfigurable architecture that can be altered "on a per clock basis" to "emulate fixed-function (hard-wired) designs" (’434 Patent, col. 4:5-7, col. 3:52-54), which differs from a processor executing a fixed instruction set.
• Technical Questions: The claim requires specific concurrent operations (e.g., the ALU operating concurrently with the multiplier). The complaint supports this with high-level block diagrams of the NEON pipeline (Compl. p. 16-19). A central factual dispute may arise over whether the accused product's pipelined execution model meets the specific "concurrent" operation required by the claim, or if the claim requires a different, more integrated form of parallelism.

V. Key Claim Terms for Construction

• The Term: "media processing unit"

• Context and Importance: This is the foundational term of claim 1. The infringement case rests on mapping this term, which the patent uses to describe its novel reconfigurable architecture, onto the accused product's ARM processor cores.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent abstract defines the invention as an apparatus where "each of the processors... may perform arithmetic-type functions, logic functions and bit manipulation functions," which aligns with the functionality of an ARM core and NEON unit (’434 Patent, Abstract). The complaint cites the patent for referring to the "aggregate of the dynamically reconfigurable computational and storage elements as a 'media processing unit'" (Compl. ¶21, citing ’434 Patent, col. 3:14-18), a functional description that Plaintiff will argue covers the accused core.
  • Evidence for a Narrower Interpretation: The specification states that the MPU's "reconfigurable routing matrix can dynamically, on a per clock basis, be switched to present a different configuration" and that its "configuration information can be changed on the fly by the nature of the data that is being processed" (’434 Patent, col. 3:52-54, col. 4:11-13). This language may support a narrower construction limited to architectures with hardware reconfigurability, as opposed to a CPU with a fixed instruction set.

• The Term: "capable of operating concurrently"

• Context and Importance: This phrase, appearing twice in claim 1, defines the required level of parallelism within each "media processing unit." Its construction will determine the technical evidence needed to prove infringement. Practitioners may focus on this term because the complaint's evidence for concurrency consists of high-level block diagrams, which may not resolve how the accused processor's pipeline technically operates.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The plain meaning of "capable of" suggests the mere existence of the physical ability, which could be met by a pipelined architecture where different functional units (e.g., multiplier, ALU) are active in the same clock cycle, albeit on different instructions. The specification's description of a complex instruction executing "three concurrent 32 bit arithmetic or logical operations in parallel" could be read as describing this capability (’434 Patent, col. 4:39-42).
  • Evidence for a Narrower Interpretation: The term could be construed to require that a single, complex instruction causes simultaneous operation in the specified units, rather than just the parallel processing of separate, simpler instructions in a standard pipeline. The patent discusses how a "complex media instruction is comparable to multiple simple DSP like instructions" (’434 Patent, col. 4:49-50), which might suggest a more tightly coupled form of concurrency than what is typical in a general-purpose processor.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain specific allegations of indirect infringement.
• Willful Infringement: The complaint does not contain specific allegations of willful infringement beyond a request for damages under 35 U.S.C. § 284 and an assertion of constructive notice (Compl. ¶36-37).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "media processing unit," which the patent describes as a novel, run-time reconfigurable architecture, be construed to cover a conventional, off-the-shelf CPU core (ARM Cortex-A9) with an integrated, fixed-instruction-set SIMD coprocessor (NEON)?
• A key evidentiary question will be one of functional proof: do the high-level block diagrams provided in the complaint sufficiently demonstrate that the accused processor’s internal units are "capable of operating concurrently" in the specific manner required by claim 1, or is there a fundamental mismatch in the technical operation that will require a more detailed microarchitectural analysis to resolve?