DCT
1:19-cv-00585
Altair Logix LLC v. Mouser Electronics Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: Mouser Electronics, Inc. (Delaware)
- Plaintiff’s Counsel: Devlin Law Firm LLC
- Case Identification: 1:19-cv-00585, D. Del., 03/28/2019
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is a Delaware corporation and therefore resides in the district for purposes of patent venue.
- Core Dispute: Plaintiff alleges that Defendant’s System-on-Module processor card, which incorporates a multi-core System-on-Chip, infringes a patent related to dynamically reconfigurable, parallel processing integrated circuits.
- Technical Context: The technology concerns System-on-Chip (SoC) architectures that aim to provide the processing performance of fixed-function hardware with the flexibility of software, a critical domain for advanced embedded systems.
- Key Procedural History: The complaint notes that the asserted patent’s claim 1 issued without amendment and was not rejected during prosecution on the basis of anticipation, a point Plaintiff may use to argue for a broad claim scope.
Case Timeline
| Date | Event |
|---|---|
| 1997-02-28 | '434 Patent Priority Date |
| 2001-09-11 | '434 Patent Issue Date |
| 2019-03-28 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
- Patent Identification: U.S. Patent No. 6,289,434, Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates, issued September 11, 2001.
The Invention Explained
- Problem Addressed: The patent describes the limitations of conventional methods for implementing functions on integrated circuits. Hard-wired, fixed-function circuits offer high performance but lack flexibility, while alternatives like microprocessors, Digital Signal Processors (DSPs), and Field Programmable Gate Arrays (FPGAs) present trade-offs in cost, performance, and complexity for real-time tasks (’434 Patent, col. 1:42-2:33). A key inefficiency in fixed-function systems is "temporal redundancy," where silicon resources are dedicated to all possible functions, even when a specific task requires only a subset, increasing cost (’434 Patent, col. 2:50-60).
- The Patented Solution: The invention proposes an apparatus featuring a plurality of “media processing units” (MPUs) that are dynamically reconfigurable at run-time. This architecture aims to reduce cost and inefficiency by "re-using groups of computational and storage elements in different configurations" to adapt to varying data and processing requirements without degrading performance (’434 Patent, col. 3:1-11). The system architecture, illustrated in the patent’s Figure 3, shows multiple MPUs interconnected with memory and peripheral interfaces on a single chip (Compl. ¶23).
- Technical Importance: This design sought to blend the high performance of application-specific hardware with the flexibility of programmable processors, a foundational concept in the evolution of System-on-Chip (SoC) technology for complex multimedia and communication applications.
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 1 ('434 Patent, Claim 1; Compl. ¶26).
- The essential elements of independent claim 1 include:
- An apparatus with an addressable memory and a plurality of media processing units (MPUs).
- Each MPU must have an input/output coupled to the memory.
- Each MPU must comprise four specific functional sub-units: a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit.
- The claim requires specific concurrent operation: the ALU must be "capable of operating concurrently" with the multiplier and arithmetic unit, and the bit manipulation unit must be "capable of operating concurrently" with the ALU and at least one of the multiplier or arithmetic unit.
- The plurality of MPUs must be capable of performing operations "simultaneously" with each other.
- An "operation" is defined as receiving an instruction and data from memory, processing the data to produce a result, and providing the result at the MPU's input/output.
III. The Accused Instrumentality
Product Identification
- Product Identification: The Critical Link MitySOM-5CSX Processor Card ("Accused Instrumentality") (Compl. ¶26).
Functionality and Market Context
- Functionality and Market Context: The Accused Instrumentality is a System-on-Module (SoM) built around an Altera Cyclone V System-on-Chip (SoC) (Compl. ¶27). The complaint alleges that the SoC's Hard Processor System, which contains a "Dual-core ARM Cortex-A9 MPCore processor," embodies the patented invention (Compl. ¶28, ¶33). Each ARM core is paired with a NEON media coprocessor, and the complaint alleges that each ARM core with its NEON coprocessor constitutes a "media processing unit" under the patent's claims (Compl. ¶28). The complaint includes a product page screenshot listing applications such as machine vision, medical imaging, and military/aerospace, positioning the product in the high-performance embedded systems market (Compl. ¶27, p. 10). A block diagram from the product's documentation shows the dual Cortex-A9 cores, labeled by Plaintiff as "Media Processors," within the Altera Cyclone V SoC (Compl. ¶28, p. 11).
IV. Analysis of Infringement Allegations
U.S. Patent No. 6,289,434 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs... | The Accused Instrumentality has a memory system (DDR3 RAM, NOR FLASH) coupled to the multicore ARM processors through multiple I/O paths. The complaint includes a block diagram highlighting this "Addressable Memory" (Compl. ¶22). | ¶27 | col. 55:21-25 |
| a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs... | The "Dual-core ARM Cortex-A9 MPCore processor" allegedly provides the plurality of media processing units, with each core acting as a unit. The complaint alleges each processor is coupled to the memory system. | ¶28 | col. 55:26-30 |
| a multiplier having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output; | The NEON media coprocessor within each ARM core allegedly comprises a multiplier (e.g., Integer MUL or FP MUL). The complaint provides a diagram from an ARM technical document showing an "Integer MUL" and "FP MUL" block within the NEON pipeline. | ¶29 | col. 55:31-36 |
| an arithmetic unit...; an arithmetic logic unit... capable of operating concurrently with at least one selected from the multiplier and arithmetic unit; | The NEON coprocessor allegedly contains an arithmetic unit (FP ADD) and an arithmetic logical unit (Integer ALU). The complaint asserts, based on information and belief, that the ALU can operate concurrently with the multiplier and arithmetic unit. The provided diagram shows these units as distinct blocks within the processor's pipeline. | ¶30-31 | col. 55:37-56:12 |
| a bit manipulation unit... capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit; | The NEON coprocessor allegedly contains a bit manipulation unit (Integer Shift unit). The complaint asserts, upon information and belief, that this unit operates concurrently with the ALU and at least one of the multiplier or arithmetic unit. | ¶32 | col. 56:13-20 |
| each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units... | The dual-core nature of the processor allegedly allows one ARM core to perform operations simultaneously with the other ARM core on the same chip. | ¶33 | col. 56:21-24 |
| each operation comprising: receiving... an instruction and data from the memory, processing the data... to produce at least one result, and providing... the at least one result at the media processor input/output. | Each ARM core allegedly receives instructions and data from memory via its NEON coprocessor, processes the data, and provides a result back to the processor's I/O. The complaint provides a diagram showing the data and instruction flow. | ¶34-35 | col. 56:25-33 |
- Identified Points of Contention:
- Scope Questions: A central dispute may arise over the definition of "media processing unit." The patent describes this unit in the context of "dynamic-adaptive run-time reconfigurable circuits" (’434 Patent, col. 1:30-31), which suggests a degree of hardware reconfigurability. The question for the court will be whether a standard, albeit powerful, CPU core like the ARM Cortex-A9 with its associated NEON coprocessor, which has a more fixed microarchitecture, falls within the scope of this term as it is used and defined in the patent.
- Technical Questions: The claim requires specific modes of concurrent operation within each media processing unit. For example, the "bit manipulation unit" must be capable of operating concurrently with the "arithmetic logic unit" and at least one of the "multiplier" or "arithmetic unit" (’434 Patent, col. 56:13-20). The complaint asserts these capabilities exist (Compl. ¶32), but the infringement analysis will depend on whether the actual micro-architectural operation of the accused NEON coprocessor supports these specific, multi-part concurrency requirements, rather than just general pipelined execution.
V. Key Claim Terms for Construction
The Term: "media processing unit"
Context and Importance: This term is the core building block of the claimed apparatus. Its construction will determine whether the accused ARM/NEON processor cores are infringing structures. Practitioners may focus on this term because the patent repeatedly emphasizes dynamic reconfigurability, which may be a point of distinction from the accused product's architecture.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Plaintiff may point to the claim language itself, which defines the unit by its constituent functional parts (multiplier, ALU, etc.) and their capabilities, arguing that any structure meeting these functional descriptions qualifies (’434 Patent, col. 55:31-56:20). The patent abstract also describes processors that perform "arithmetic-type functions, logic functions and bit manipulation functions," a general description that could encompass the accused ARM/NEON cores (’434 Patent, Abstract).
- Evidence for a Narrower Interpretation: Defendant may argue that the term must be read in light of the specification's repeated emphasis on overcoming the limitations of fixed-function devices through "dynamic-adaptive run-time reconfigurable circuits" and by "re-using groups of computational and storage elements in different configurations" (’434 Patent, col. 1:30-31, col. 3:2-4). This could support a narrower construction requiring a level of hardware reconfigurability beyond that of a standard CPU core.
The Term: "capable of operating concurrently"
Context and Importance: This phrase appears twice in Claim 1 and governs the required parallelism between the internal functional units of each MPU. The outcome of the infringement analysis may depend on whether the accused processor's pipelined execution meets this limitation.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue that this term should be given its plain meaning in the context of processor design, where functional units operating in the same clock cycles within a pipeline are considered concurrent. The patent itself describes its invention in the context of pipelining (’434 Patent, col. 13:49-53).
- Evidence for a Narrower Interpretation: A party could argue that the claim's specific combination of concurrent operations (e.g., ALU with both multiplier and arithmetic unit) requires more than just standard pipelining and implies a capacity for true simultaneous, independent execution of these specific unit combinations, raising the evidentiary bar for infringement.
VI. Other Allegations
The complaint does not contain counts for indirect or willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: Can the term "media processing unit," which is rooted in the patent's disclosure of "dynamic-adaptive run-time reconfigurable circuits," be construed to cover the more conventional, fixed-microarchitecture design of the accused ARM Cortex-A9 processor core and its NEON coprocessor?
- A key evidentiary question will be one of technical operation: Does the accused NEON coprocessor's actual operation meet the specific, multi-part concurrency limitations recited in Claim 1, or is there a functional mismatch? The resolution will likely require detailed evidence of the processor's microarchitecture beyond the high-level block diagrams presented in the complaint.