Invensas Corp v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Invensas Corporation (Delaware) and Tessera Advanced Technologies, Inc. (Delaware)
  • Defendant: NVIDIA Corporation (Delaware)
  • Plaintiff’s Counsel: Farnan LLP; Covington & Burling LLP
• Case Identification: 1:19-cv-00861, D. Del., 05/08/2019
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because the Defendant, NVIDIA, is a Delaware corporation and has allegedly committed acts of infringement in the state.
• Core Dispute: Plaintiffs allege that Defendant’s Graphics Processing Units (GPUs) and System-on-a-Chip (SoC) processors infringe five patents related to semiconductor manufacturing methods, device packaging structures, and circuit design.
• Technical Context: The patents address fundamental challenges in modern semiconductor technology, including achieving surface planarity during manufacturing, advanced multi-chip packaging, and ensuring stable circuit performance across different temperatures.
• Key Procedural History: The complaint alleges that Plaintiffs provided Defendant with notice and exemplary infringement claim charts for U.S. Patent Nos. 6,232,231 and 6,849,946 on December 2, 2014; for U.S. Patent No. 6,317,333 on October 13, 2014; and for U.S. Patent No. 5,666,046 on February 11, 2015. For U.S. Patent No. 7,064,005, knowledge is alleged from the date of the complaint's filing. Public records indicate that subsequent to the filing of this complaint, the asserted claims of the '231 and '946 patents were cancelled in inter partes review (IPR) proceedings, a development that may significantly affect the scope of the litigation.

Case Timeline

Date	Event
1995-08-24	’046 Patent Priority Date
1997-08-28	’333 Patent Priority Date
1997-09-09	’046 Patent Issue Date
1998-08-31	’231 & ’946 Patents Priority Date
2001-05-15	’231 Patent Issue Date
2001-05-14	’005 Patent Priority Date
2001-11-13	’333 Patent Issue Date
2005-02-01	’946 Patent Issue Date
2006-06-20	’005 Patent Issue Date
2014-10-13	Alleged notice to NVIDIA regarding ’333 Patent
2014-12-02	Alleged notice to NVIDIA regarding ’231 and ’946 Patents
2015-02-11	Alleged notice to NVIDIA regarding ’046 Patent
2019-05-08	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,232,231 - "Planarized Semiconductor Interconnect Topography and Method For Polishing a Metal Layer To Form Interconnect," issued May 15, 2001

The Invention Explained

• Problem Addressed: In multi-layer integrated circuits, chemical-mechanical polishing (CMP) is used to create flat surfaces for subsequent layers. However, this process can cause "dishing," where wide metal features (like bond pads) are excessively polished down relative to surrounding areas, and "oxide erosion," where dense arrays of narrow features become recessed. These surface disparities can compromise device reliability and performance (US 6232231 B1, col. 2:30-45).
• The Patented Solution: The invention proposes a method to improve polishing uniformity by etching non-functional "dummy trenches" into the dielectric layer in areas that would otherwise be large, open spaces, such as between a wide interconnect and a series of narrow interconnects. These dummy trenches, when filled with metal along with the functional trenches, provide structural support to the polishing pad, preventing it from flexing into and "dishing" the wide features, resulting in a more globally planar surface (US 6232231 B1, col. 4:32-44; Fig. 5).
• Technical Importance: Achieving high planarity is critical for reliably manufacturing complex, multi-layered chips with increasingly fine features, as it directly impacts photolithography accuracy and interconnect integrity (US 6232231 B1, col. 1:44-51).

Key Claims at a Glance

• The complaint asserts independent method claim 1 (Compl. ¶27).
• Essential elements of claim 1 include:
  • etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, where the first trench is wider than the second trenches;
  • filling the dummy, first, and second trenches with a conductive material;
  • polishing the conductive material to form dummy conductors exclusively in the dummy trenches and interconnect exclusively in the first and second trenches;
  • wherein the resulting dummy conductors are electrically separate from underlying conductive features and co-planar with the interconnect.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,849,946 - "Planarized Semiconductor Interconnect Topography and Method For Polishing a Metal Layer To Form Interconnect," issued February 1, 2005

The Invention Explained

• Problem Addressed: As with the related ’231 patent, this invention addresses the problem of non-uniform surfaces resulting from CMP, particularly the "dishing" of wide metal lines and "erosion" in dense regions (US6849946B2, col. 3:1-24).
• The Patented Solution: The patent claims the resulting physical structure, or topography, that is created by using dummy features. It describes a semiconductor topography with a specific geometric arrangement: a wide trench and narrow trenches containing conductive lines, with intermediate-width dummy conductors situated between them. This structure is designed to be inherently planar, with the upper surfaces of the dummy conductors and the functional conductive lines being "substantially coplanar" (US6849946B2, col. 4:30-44; Fig. 7).
• Technical Importance: By defining the desired physical structure, this patent provides a target for manufacturing processes aiming to overcome CMP-related defects and improve yield for high-density devices (US6849946B2, col. 4:45-53).

Key Claims at a Glance

• The complaint asserts independent product claim 16 (Compl. ¶45).
• Essential elements of claim 16 include:
  • a plurality of laterally spaced dummy trenches in a dielectric layer, between a first trench and a series of second trenches;
  • each of the second trenches is relatively narrow compared to the first trench;
  • a lateral dimension of at least one dummy trench is less than the first trench's dimension and greater than the second trench's dimension;
  • dummy conductors in the dummy trenches that are electrically separate from features below;
  • conductive lines in the first and second trenches, wherein their upper surfaces are substantially coplanar with the dummy conductor upper surfaces.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,064,005 - "Semiconductor Apparatus and Method of Manufacturing Same," issued June 20, 2006

• Technology Synopsis: The patent describes a method for manufacturing a multi-chip module. The method involves forming embedded electrodes (akin to Through-Silicon Vias or TSVs) that pass through a wafer, which serves as an interposer substrate. Device chips are flip-chip mounted on one side of the interposer, and the other side is ground down to expose the embedded electrodes for connection to a larger package or board (US7064005B2, Abstract; col. 2:46-51).
• Asserted Claims: The complaint asserts independent method claim 1 (Compl. ¶60).
• Accused Features: The complaint accuses NVIDIA's CoWoS (Chip-on-Wafer-on-Substrate) GPUs, such as the Tesla P100 and V100, which allegedly use a passive silicon interposer with embedded electrodes to connect GPU and memory dies (Compl. ¶¶ 61-62).

U.S. Patent No. 6,317,333 - "Package Construction of Semiconductor Device," issued November 13, 2001

• Technology Synopsis: This patent discloses a package construction for a semiconductor device, specifically a Ball Grid Array (BGA) substrate. The substrate is built with a multi-layer structure—comprising upper, intermediate, and lower insulating layers—where the intermediate "core" layer is made of a material with thermal expansion characteristics that substantially match the circuit board it will be mounted on. This design aims to reduce mechanical stress and prevent peeling or disconnection caused by thermal mismatch during operation (US 6317333 B1, Abstract; col. 2:40-47).
• Asserted Claims: The complaint asserts independent product claim 1 (Compl. ¶75).
• Accused Features: The complaint accuses NVIDIA's Tesla K10, Grid K2, and MSI's GeForce GTX 750 Ti graphics cards of infringing. These products are alleged to comprise a GPU in a BGA substrate package with a core layer and build-up layers whose thermal properties match the claimed structure (Compl. ¶¶ 76-77).

U.S. Patent No. 5,666,046 - "Reference Voltage Circuit Having a Substantially Zero Temperature Coefficient," issued September 9, 1997

• Technology Synopsis: The patent describes a method and circuit for generating a stable reference voltage that does not change with temperature (a "bandgap reference"). It achieves this by generating a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and then summing them to create an output current (and corresponding voltage) with a substantially zero temperature coefficient (US 5666046, Abstract). This is a fundamental building block for analog and mixed-signal circuits.
• Asserted Claims: The complaint asserts independent method claim 20 (Compl. ¶90).
• Accused Features: The complaint accuses NVIDIA's Kepler GK107 GPU and Tegra 3 devices. These products allegedly contain circuitry that generates and sums currents with opposing temperature coefficients to produce a stable reference voltage (Compl. ¶¶ 91-95).

III. The Accused Instrumentality

• Product Identification: The complaint broadly accuses NVIDIA's GPUs and SoCs, including specific product families such as the 40nm Fermi GPUs, 28nm Kepler GPUs, 28nm Maxwell GPUs, 16nm Pascal GPUs, 28nm and 20nm Tegra SoCs, and CoWoS GPUs (Compl. ¶¶ 13-19, 28, 46, 61, 76, 91).
• Functionality and Market Context: The accused products are high-performance semiconductor devices that form the core of NVIDIA's business segments. The complaint references an NVIDIA 10-K form, which is depicted in a visual, to show these segments include "GeForce for PC gaming," "Tesla for AI," and "DRIVE automotive supercomputers" (Compl. ¶8; Compl. p. 3). These products are central to markets for PC gaming, professional design, data centers, and automotive computing (Compl. ¶8). The complaint alleges NVIDIA does not directly manufacture the semiconductor wafers, instead using a "fabless" model with third-party suppliers like Taiwan Semiconductor Manufacturing Company ("TSMC") (Compl. ¶9).

IV. Analysis of Infringement Allegations

’231 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches...	The accused products are made by a process that includes etching multiple dummy trenches in a dielectric layer between a wider first interconnect trench and narrower second interconnect trenches.	¶31	col. 4:12-19
filling said dummy trenches and said first and second trenches with a conductive material...	The manufacturing process allegedly fills the etched dummy, first, and second trenches with a conductive material, such as copper.	¶33	col. 4:22-29
polishing said conductive material to form dummy conductors exclusively in said dummy trenches and interconnect exclusively in said first and second trenches...	The process allegedly includes polishing the deposited conductive material until it is exclusively within the various trenches, separating the dummy conductors from the interconnects.	¶34	col. 4:29-32
wherein said dummy conductors are electrically separate from said plurality of electrically conductive features and co-planar with said interconnect.	In the final accused products, the dummy conductors are allegedly co-planar with the interconnects but are electrically separate from underlying active or passive components.	¶35	col. 4:33-38

’946 Patent Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a plurality of laterally spaced dummy trenches in a dielectric layer, between a first trench and a series of second trenches...	The accused products allegedly comprise a structure with multiple dummy trenches in an insulating material located between a relatively wide trench and a series of narrower trenches.	¶48	col. 8:12-16
a lateral dimension of at least one of the laterally spaced dummy trenches is less than a lateral dimension of the first trench and greater than a lateral dimension of at least one of the series of second trenches...	The width of one or more of the dummy trenches is alleged to be less than the width of the wide trench and greater than the width of the narrow trenches.	¶49	col. 8:17-21
dummy conductors in said laterally spaced dummy trenches and electrically separate from electrically conductive features below said dummy conductors...	The accused products allegedly contain dummy conductors (e.g., copper-based) that are electrically separate from both the main interconnects and any underlying active components.	¶50	col. 8:22-25
conductive lines in said series of second trenches and said first trench, wherein upper surfaces of said conductive lines are substantially coplanar with dummy conductor upper surfaces.	The upper surfaces of the copper-based interconnects in the wide and narrow trenches are alleged to be substantially coplanar with the upper surfaces of the dummy conductors.	¶51	col. 8:26-29

Identified Points of Contention

• Factual/Evidentiary Question: For the '231 and '946 patents, the allegations are directed at the physical structure of semiconductor devices and the methods used to make them. Since NVIDIA is fabless, a central question is what evidence Plaintiffs can obtain to prove that the manufacturing processes of third-party foundries like TSMC practice the claimed methods and create the claimed structures. The complaint relies on "information and belief" for these core technical allegations (Compl. ¶¶ 31, 48).
• Scope Questions: The dispute may turn on the scope of relative terms. For the '946 patent, a key question is what degree of planarity is required to meet the "substantially coplanar" limitation. For the '231 patent, a question is whether any feature added to a layout for process reasons (e.g., metal fill for density rules) meets the definition of a "dummy trench" as taught in the patent.

V. Key Claim Terms for Construction

For the ’231 Patent

• The Term: "dummy trenches"
• Context and Importance: This term is the core of the invention. Its definition is critical because infringement hinges on whether the accused manufacturing process creates features that qualify as "dummy trenches" for the purpose of improving planarization, as opposed to other structures that might exist for different reasons (e.g., electrical shielding or satisfying process design rules).
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the purpose of the features is to "improve the planarization of the interconnect level" (US 6232231 B1, col. 4:39-40). This functional language may support a construction that includes any feature added to an otherwise open area to improve polishing uniformity, regardless of its precise shape or layout.
  • Evidence for a Narrower Interpretation: The patent consistently depicts the "dummy trenches" in specific arrangements, such as being placed "between a relatively wide trench and a series of relatively narrow trenches" (US 6232231 B1, Abstract; Fig. 5). This could support a narrower construction requiring this specific positional relationship. The term "dummy" itself implies a non-functional nature, which could be used to narrow the scope.

For the ’946 Patent

• The Term: "substantially coplanar"
• Context and Importance: This term is crucial for determining infringement of claim 16, as it defines the required physical relationship between the functional interconnects and the dummy conductors. Because perfect planarity is unachievable, the scope of "substantially" will determine if the accused products, which may have some level of surface variation, fall within the claim.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The background describes the problem of "dishing" and "recessed" areas, suggesting that "substantially coplanar" should be interpreted as a topography that is sufficiently flat to avoid these specific, detrimental effects, allowing for some minor, non-problematic variation (US6849946B2, col. 3:1-24).
  • Evidence for a Narrower Interpretation: The patent figures, such as Figure 7, depict an idealized, perfectly flat surface across the dummy conductors (68) and interconnect (72). A defendant may argue that these depictions define the scope and that "substantially" only allows for de minimis, unintentional process variations from this ideal.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all asserted patents. It claims NVIDIA encourages infringement by third parties (OEMs, ODMs, system builders, etc.) through the provision of marketing materials, technical specifications, datasheets, user manuals, and development resources on its website. The complaint also points to the "NVIDIA Partner Network" as a mechanism for assisting and encouraging customers to integrate and use the accused products in an infringing manner (Compl. ¶¶ 37, 52, 68, 82, 97).
• Willful Infringement: The complaint alleges willful infringement for all five patents. For the '231, '946, '333, and '046 patents, willfulness is based on alleged pre-suit knowledge stemming from notice and the provision of claim charts dating back to 2014 and 2015 (Compl. ¶¶ 26, 44, 74, 89). For the '005 patent, willfulness is based on knowledge NVIDIA gained "since at least the filing of this Complaint" (Compl. ¶59).

VII. Analyst’s Conclusion: Key Questions for the Case

1. Viability of Claims: A threshold issue for the '231 and '946 patents is their viability, as public records show the asserted claims were cancelled in inter partes review proceedings after the complaint was filed. The court will need to address the legal effect of these cancellations on the pending infringement counts.
2. Evidentiary Proof of Manufacturing: For the remaining patents on semiconductor structure and methods ('005 and '333), a central question will be evidentiary. Can Plaintiffs develop factual proof, beyond the initial "information and belief" pleading standard, that the specific internal structures and third-party manufacturing processes used for NVIDIA's products meet every limitation of the asserted claims?
3. Claim Construction and Technical Mismatch: For the circuit design patent ('046), the case will likely focus on claim construction and technical operation. A key question will be one of functional equivalence: does the accused reference voltage circuitry in NVIDIA's chips operate by "generating a first current having a positive temperature coefficient" and a second with a negative one, and then "summing" them, as specifically required by the claim, or does it achieve a stable voltage through a different, non-infringing technical method?