DCT
1:19-cv-00996
Cedar Lane Tech Inc v. Photonics Management Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Cedar Lane Technologies Inc. (Canada)
- Defendant: Photonics Management Corp. (Delaware)
- Plaintiff’s Counsel: DEVLIN LAW FIRM LLC
- Case Identification: 1:19-cv-00996, D. Del., 05/30/2019
- Venue Allegations: Venue is alleged to be proper as Defendant is incorporated in Delaware and has committed acts of patent infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s digital slide scanner products infringe patents related to methods and systems for interfacing image sensors with data compression hardware and host computer systems.
- Technical Context: The technology concerns efficient management of digital image data as it moves from a sensor to a processing or compression unit, a critical function in high-performance imaging systems like digital cameras and scanners.
- Key Procedural History: The complaint does not note any prior litigation, post-grant proceedings, or licensing history. U.S. Patent No. 8,537,242 is a divisional of the application that matured into U.S. Patent No. 6,972,790, indicating a shared specification between the two patents.
Case Timeline
| Date | Event |
|---|---|
| 1999-06-01 | '527 Patent Priority Date |
| 2000-01-21 | '790 Patent Priority Date |
| 2000-01-21 | '242 Patent Priority Date |
| 2002-10-29 | '527 Patent Issue Date |
| 2005-12-06 | '790 Patent Issue Date |
| 2013-09-17 | '242 Patent Issue Date |
| 2019-05-30 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued October 29, 2002
The Invention Explained
- Problem Addressed: The patent describes a problem in conventional digital imaging systems where an "extra memory" device, such as a RAM chip, is required to sit between the analog-to-digital (A/D) converter and the JPEG compression chip ('527 Patent, col. 1:47-52). This extra component is needed to buffer and reformat the line-by-line data stream from the image sensor into the block-based (e.g., 8x8 pixel) format required by the JPEG algorithm, adding cost and complexity to the device ('527 Patent, col. 1:52-57).
- The Patented Solution: The invention proposes an interface module that eliminates the need for this separate, external memory chip ('527 Patent, col. 1:58-64). The module includes its own internal memory, sized specifically to hold a "predetermined number of image lines" (e.g., eight lines) sufficient to form a compression unit ('527 Patent, col. 3:1-8). The module reads these lines from the A/D converter, stores them, and then feeds properly formatted image blocks directly to the JPEG compression device, thereby streamlining the hardware design ('527 Patent, Abstract; Fig. 2).
- Technical Importance: This memory management approach was intended to reduce the component cost, physical size, and design complexity of devices like digital scanners and cameras by integrating the buffering function more efficiently. ('527 Patent, col. 2:20-24).
Key Claims at a Glance
- The complaint asserts independent method claim 8 (Compl. ¶15).
- The essential elements of independent claim 8 include:
- sequentially reading a predetermined number of image lines from the image data output of said analog/digital converting means;
- storing said predetermined number of image lines in memory means, said memory means capable of storing the same number of image lines as said built-in memory device; and
- sequentially reading a predetermined size of image block from said memory means to said built-in memory device when said image data output is determined to be compressed.
- The complaint reserves the right to assert additional claims (Compl. ¶15).
U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued December 6, 2005
The Invention Explained
- Problem Addressed: The patent addresses the technical incompatibility between the continuous, high-speed, "video style" data stream produced by a CMOS image sensor and the command-based, random-access nature of a general-purpose microprocessor ('790 Patent, col. 1:47-53). Bridging this gap conventionally required "additional glue logic" and external memory, which negated the cost and integration benefits of using CMOS sensor technology ('790 Patent, col. 1:62-64).
- The Patented Solution: The patent describes an on-chip interface that decouples the image sensor from the host processor. This interface uses a memory, such as a first-in-first-out (FIFO) buffer, to store data from the imaging array at the sensor's rate ('790 Patent, col. 2:6-9). In response to the "quantity of data in the memory" reaching a certain point, a signal generator alerts the host processor (e.g., via an interrupt), which can then read the buffered data at its own, different rate ('790 Patent, Abstract; col. 2:9-14).
- Technical Importance: By creating an asynchronous buffer between the sensor and processor, the invention allows the processor to perform other tasks and retrieve image data when convenient, simplifying system design and fully leveraging the integration potential of CMOS technology. ('790 Patent, col. 3:23-28).
Key Claims at a Glance
- The complaint asserts independent apparatus claim 1 (Compl. ¶24).
- The essential elements of independent claim 1 include:
- a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals;
- a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory; and
- a circuit for controlling the transfer of the data from the memory at a rate determined by the processor system.
- The complaint reserves the right to assert additional claims (Compl. ¶24).
U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," issued September 17, 2013
Technology Synopsis
As a divisional of the application for the '790 Patent, this patent shares a common specification and addresses the same technical problem of interfacing an image sensor with a host system ('242 Patent, col. 1:1-5). The claims are directed toward an interface that stores image data and, upon the quantity of data reaching a predetermined level, generates a bus request signal to a bus arbitration unit, facilitating data transfer without necessarily interrupting the main CPU ('242 Patent, Abstract).
Asserted Claims
The complaint asserts independent claims 1 and 8 (Compl. ¶33).
Accused Features
The complaint alleges that the accused products' functionality for managing the transfer of image data from the sensor to the host system infringes this patent (Compl. ¶33, ¶38).
III. The Accused Instrumentality
Product Identification
The complaint names the "Photonics' NanoZoomer S360" as the "Exemplary Photonics Products" (Compl. ¶15).
Functionality and Market Context
The complaint identifies the accused product as a digital slide scanner but provides no specific details regarding its internal architecture or operation (Compl. ¶15). The infringement allegations are based on claim charts, provided as exhibits to the complaint, which purportedly detail how the accused product functions (Compl. ¶20, ¶29, ¶38). The complaint does not contain allegations regarding the product's specific market positioning. No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint's infringement allegations rely on incorporating by reference external claim chart exhibits that were not filed as part of the public document. The analysis below is based on the complaint's narrative assertions that the accused products practice the claimed technology.
'527 Patent Infringement Allegations
| Claim Element (from Independent Claim 8) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| sequentially reading a predetermined number of image lines from the image data output of said analog/digital converting means; | The complaint alleges the NanoZoomer S360 performs this function, incorporating by reference the analysis in Exhibit 4. | ¶20, ¶21 | col. 4:36-39 |
| storing said predetermined number of image lines in memory means, said memory means capable of storing the same number of image lines as said built-in memory device; | The complaint alleges the NanoZoomer S360 includes a memory means that performs this storing function, incorporating by reference the analysis in Exhibit 4. | ¶20, ¶21 | col. 4:40-44 |
| and sequentially reading a predetermined size of image block from said memory means to said built-in memory device when said image data output is determined to be compressed. | The complaint alleges the NanoZoomer S360 reads image blocks from its memory for compression, incorporating by reference the analysis in Exhibit 4. | ¶20, ¶21 | col. 4:45-49 |
- Identified Points of Contention:
- Technical Questions: A primary question will be whether the NanoZoomer S360's architecture includes a memory that functions as claimed. Specifically, is there evidence that its buffer is sized to store a number of image lines corresponding to the dimensions of a compression unit, for the express purpose of obviating a separate, larger memory for that reformatting task?
- Scope Questions: The term "memory means" in claim 8 is a means-plus-function limitation. Its scope will be limited to the structure disclosed in the specification for performing the storing function ("memory device 24") and its equivalents. A dispute may arise over whether the memory architecture in the accused product is structurally equivalent to the specific implementation in the '527 patent.
'790 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals; | The complaint alleges the NanoZoomer S360 contains a memory that performs this function, incorporating by reference the analysis in Exhibit 5. | ¶29, ¶30 | col. 8:1-5 |
| a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory; | The complaint alleges the NanoZoomer S360 has a signal generator triggered by data quantity, incorporating by reference the analysis in Exhibit 5. | ¶29, ¶30 | col. 8:10-13 |
| and a circuit for controlling the transfer of the data from the memory at a rate determined by the processor system. | The complaint alleges the NanoZoomer S360 has a control circuit for this purpose, incorporating by reference the analysis in Exhibit 5. | ¶29, ¶30 | col. 8:14-17 |
- Identified Points of Contention:
- Technical Questions: The infringement analysis will turn on whether the accused product's signaling mechanism is in fact triggered "in response to the quantity of data in the memory." Evidence would be required to show a causal link, such as a hardware counter or software logic that monitors the buffer's fill level and generates an interrupt or bus request upon reaching a threshold.
- Scope Questions: Does the accused product's data transfer mechanism operate "at a rate determined by the processor system"? This raises the question of whether the processor-side control of the data read-out from the buffer in the accused device matches the functionality described in the patent.
V. Key Claim Terms for Construction
Term ('790 Patent, Claim 1): "in response to the quantity of data in the memory"
- Context and Importance: This phrase is central to the novelty of the invention and the infringement analysis for the '790 and '242 patents. It defines the trigger for alerting the host system. The case may depend on whether the accused product's signaling is merely sequential or is specifically responsive to the buffer's fill state.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The abstract states the signal is generated "In response to the quantity of data in the memory" without further limitation, which may support a more general reading ('790 Patent, Abstract).
- Evidence for a Narrower Interpretation: The detailed description discloses a specific embodiment where an "increment/decrement counter" (54) tracks the writes and reads, and an "interrupt generator" (48) compares the counter's output to a pre-set "FIFO limit signal" (Sl) to trigger the interrupt ('790 Patent, col. 6:11-15; Fig. 2). This specific implementation may be used to argue for a narrower construction requiring a direct comparison to a data quantity threshold.
Term ('527 Patent, Claim 8): "memory means"
- Context and Importance: As a means-plus-function term, its scope is defined by the corresponding structure in the specification. Practitioners may focus on this term because the infringement case depends on whether the accused product's memory architecture is structurally equivalent to the patent's disclosed "memory device 24" ('527 Patent, Fig. 2).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification refers to the memory device as potentially being a "random access memory" ('527 Patent, col. 2:50-51), which a party might argue broadens the scope of equivalent structures.
- Evidence for a Narrower Interpretation: The claim itself and the specification repeatedly tie the function and capability of the memory means to storing "the same number of image lines as said built-in memory device" of the JPEG compressor (e.g., 8 lines for an 8x8 pixel block) ('527 Patent, col. 4:40-44, col. 3:4-8). This linkage to the specific purpose of creating a compression block could support a narrower definition that excludes general-purpose system memory.
VI. Other Allegations
- Indirect Infringement: For all three patents, the complaint alleges induced infringement based on Defendant selling the accused products and distributing "product literature and website materials" that allegedly instruct customers on how to use the products in an infringing manner (Compl. ¶18, ¶27, ¶36). The complaint also pleads contributory infringement, alleging the products are a material part of the infringement and not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶19, ¶28, ¶37).
- Willful Infringement: The complaint alleges that its filing constitutes "notice and actual knowledge" of the patents-in-suit (Compl. ¶16, ¶25, ¶34). It further alleges that Defendant's continued infringing activities after this date are willful, which may form the basis for a claim for enhanced damages (Compl. ¶17, ¶26, ¶35).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of architectural correspondence: Does the internal data-handling architecture of the NanoZoomer S360, once revealed in discovery, actually map onto the specific buffering and signaling schemes recited in the patents? For the '527 patent, this requires a buffer sized and used for the specific purpose of block-based reformatting, while for the '790 and '242 patents, it requires a signal generator specifically triggered by the quantity of data in that buffer.
- The case will also present a key evidentiary question: As the complaint relies entirely on incorporating non-public exhibits, the litigation will turn on the technical evidence Plaintiff can produce to prove that the accused product's hardware and software perform the functions required by each claim element. A failure to show, for example, that the processor alert is causally linked to the buffer's fill level would undermine the infringement allegations for the '790 patent family.