DCT

1:19-cv-01006

PACT XPP Schweiz AG v. Intel Corp

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-01006, D. Del., 05/30/2019
  • Venue Allegations: Venue is asserted on the basis that Intel is a Delaware corporation and has committed acts of infringement in the district. The complaint also notes the action is a refiling based on a parties' stipulation following a dismissal of a prior complaint.
  • Core Dispute: Plaintiff alleges that Defendant’s multi-core processors, including the Core, Xeon, and Celeron series, infringe twelve patents related to multi-core processor architecture, bus systems, dynamic clock frequency adjustment, and 3D chip stacking.
  • Technical Context: The technology concerns fundamental aspects of modern multi-core microprocessor design, a critical domain for performance and power efficiency in computing devices from consumer laptops to enterprise-level servers.
  • Key Procedural History: The complaint alleges that Intel had pre-suit knowledge of the asserted patents and its infringement, at least as of the service of a complaint in a prior lawsuit, [PACT XPP Schweiz AG](https://ai-lab.exparte.com/party/pact-xpp-schweiz-ag) v. Intel Corp, 1:19-cv-00267 (DED), which was originally filed on February 7, 2019. This prior action is central to the plaintiff's allegations of willful infringement.

Case Timeline

Date Event
2000-06-13 Earliest Priority Date ('872 Patent)
2001-03-05 Earliest Priority Date ('301 and '605 Patents)
2001-03-07 Earliest Priority Date ('047 Patent)
2001-08-16 Earliest Priority Date ('812 Patent)
2001-09-11 Earliest Priority Date ('807 and '631 Patents)
2001-09-19 Earliest Priority Date ('549 Patent)
2001-10-08 Earliest Priority Date ('593 Patent)
2001-12-14 Earliest Priority Date ('505 Patent)
2002-09-06 Earliest Priority Date ('763 Patent)
2011-01-01 Accused Intel "Sandy Bridge" architecture launched
2011-01-01 Accused Intel "Turbo Boost 2.0" technology launched
2011-04-19 U.S. Patent No. 7,928,763 Issues
2012-10-30 U.S. Patent No. 8,301,872 Issues
2012-11-13 U.S. Patent No. 8,312,301 Issues
2013-06-25 U.S. Patent No. 8,471,593 Issues
2014-04-01 U.S. Patent No. 8,686,549 Issues
2014-08-26 U.S. Patent No. 8,819,505 Issues
2015-05-19 U.S. Patent No. 9,037,807 Issues
2015-07-07 U.S. Patent No. 9,075,605 Issues
2015-10-27 U.S. Patent No. 9,170,812 Issues
2016-01-01 Accused Intel "Turbo Boost Max 3.0" technology launched
2016-02-02 U.S. Patent No. 9,250,908 Issues
2016-09-06 U.S. Patent No. 9,436,631 Issues
2017-01-01 Accused Intel "mesh bus" architecture introduced
2017-01-24 U.S. Patent No. 9,552,047 Issues
2018-12-01 Accused Intel "Foveros" technology announced
2019-01-01 Accused Intel "Lakefield" product announced
2019-02-07 Original Complaint filed in D. Del.
2019-05-30 Current Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,928,763 - "Multi-Core Processing System"

  • Patent Identification: U.S. Patent No. 7928763, "Multi-Core Processing System," issued April 19, 2011.

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of efficiently executing data processing steps that are traditionally best suited for sequential processor architectures (like sequencers) within a reconfigurable, parallel processing environment ('763 Patent, col. 2:5-20).
  • The Patented Solution: The invention proposes a "cell element field" where function cells (e.g., ALUs) and memory cells are combined. A key feature is a direct "control connection" from a function cell to an associated memory cell, which allows the function cell to manage memory access for addresses and data ('763 Patent, col. 2:21-34). This creates a "function cell-memory cell combination" that can emulate the behavior of a traditional sequencer within a parallel, reconfigurable architecture ('763 Patent, Abstract; Fig. 2a).
  • Technical Importance: This architecture aimed to merge the high throughput of parallel processing with the efficiency required for sequential tasks, a foundational challenge in the design of versatile multi-core processors (Compl. ¶¶8-9).

Key Claims at a Glance

  • The complaint asserts infringement of at least independent claim 1 (Compl. ¶38).
  • Claim 1 requires:
    • A multi-processor chip comprising:
    • a plurality of data processing cells, each adapted for sequentially executing algebraic and logic functions and having at least one arithmetic logic unit, data register file, program pointer, and instruction decoder;
    • a plurality of memory cells;
    • at least one interface unit;
    • at least one Memory Management Unit (MMU); and
    • a bus system for interconnecting the cells and interface unit, wherein the bus system is adapted for programmably interconnecting at runtime at least one of the data processing cells and memory cells with at least one of the memory cells and interface unit.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,301,872 - "Pipeline Configuration Protocol and Configuration Unit Communication"

  • Patent Identification: U.S. Patent No. 8301872, "Pipeline Configuration Protocol and Configuration Unit Communication," issued October 30, 2012.

The Invention Explained

  • Problem Addressed: The patent’s background describes the need for efficient data communication and reconfiguration protocols in cellular data processing structures, such as multi-core processors ('872 Patent, col. 1:29-51).
  • The Patented Solution: The invention describes a microprocessor architecture with multiple processor cores and a multi-level cache system ('872 Patent, Abstract). A key aspect is a bus system that interconnects a plurality of "superior cache level" nodes (e.g., shared L3 caches) to each other and to the processor cores. The patent specifies that these cache nodes are connected to multiple segments of the bus system and are capable of "relaying data" from one bus segment to another, enabling efficient data transfer across the chip ('872 Patent, Abstract; col. 4:50-67).
  • Technical Importance: This solution provides a scalable method for interconnecting an increasing number of processor cores with a shared, distributed cache, which is a fundamental requirement for modern multi-core CPU performance and data coherency (Compl. ¶¶9-10).

Key Claims at a Glance

  • The complaint asserts infringement of at least independent claim 2 (Compl. ¶62).
  • Claim 2 requires:
    • A microprocessor chip comprising a plurality of processor cores;
    • a cache system with multiple levels, including a first cache level and a superior cache level with a plurality of same-level cache nodes;
    • a bus system;
    • wherein a respective first-level cache is dedicated to each processor core;
    • the bus interconnects the cache nodes to each other and to the processor cores;
    • each cache node is connectable to each core for data transfer;
    • a highest cache level is connected to a higher-level memory; and
    • each cache node is connected to at least two bus segments and is capable of relaying data between those segments.
  • The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsules

  • Multi-Patent Capsule: U.S. Patent No. 8312301

    • Patent Identification: U.S. Patent No. 8,312,301, "Methods and Devices for Treating and Processing Data," issued November 13, 2012.
    • Technology Synopsis: This patent relates to managing processor workloads by distributing different "code sections" (e.g., applications) to different groups of processing elements (e.g., cores) and assigning a respective clock frequency to each group, allowing for dynamic performance and power management (Compl. ¶¶92-94).
    • Asserted Claims: At least independent claim 10 (Compl. ¶89).
    • Accused Features: Intel’s Turbo Boost Max Technology 3.0, which allegedly manages the distribution of applications to cores running at different clock frequencies (Compl. ¶¶88, 92-94).

  • Multi-Patent Capsule: U.S. Patent No. 8471593

    • Patent Identification: U.S. Patent No. 8,471,593, "Logic Cell Array and Bus System," issued June 25, 2013.
    • Technology Synopsis: The patent describes a multi-core processor with a bus system having dedicated structures for bi-directional data transfer. It further claims that each processing core has a physically dedicated connection to an assigned memory unit (e.g., an LLC slice), which is also accessible by other cores via a secondary path on the bus system (Compl. ¶¶118-119).
    • Asserted Claims: At least independent claim 1 (Compl. ¶112).
    • Accused Features: Intel's ring bus architecture, which is alleged to have structures for bi-directional data transfer and to provide each core with a dedicated connection to a physically assigned LLC slice (Compl. ¶¶117-119).

  • Multi-Patent Capsule: U.S. Patent No. 8686549

    • Patent Identification: U.S. Patent No. 8,686,549, "Reconfigurable Elements," issued April 1, 2014.
    • Technology Synopsis: This patent addresses 3D chip stacking, describing a device with at least two stacked dies. Programmable data processing units (e.g., CPUs) are on a first die, while an "interconnect structure" (e.g., an active interposer) is implemented on a second die to connect the processing units (Compl. ¶¶138-140, 143-144).
    • Asserted Claims: At least independent claim 39 (Compl. ¶136).
    • Accused Features: Intel's "Foveros" 3D packaging technology and products like "Lakefield" that implement it, which allegedly stack a "Computer Chip" die on an "Active Interposer" die (Compl. ¶¶136, 138-139).

  • Multi-Patent Capsule: U.S. Patent No. 8819505

    • Patent Identification: U.S. Patent No. 8,819,505, "Data Processor Having Disabled Cores," issued August 26, 2014.
    • Technology Synopsis: The patent describes an integrated circuit where more processing cores are implemented on the chip than are actually used. This allows defective cores, identified during a "chip test," to be exempted from data transfer via the bus system, improving manufacturing yields (Compl. ¶¶165, 167).
    • Asserted Claims: At least independent claim 27 (Compl. ¶161).
    • Accused Features: Intel multi-core processors, particularly Xeon processors with nine or more cores, which allegedly disable certain cores due to manufacturing defects and exempt them from data transfer via the ring bus (Compl. ¶¶165, 167).

  • Multi-Patent Capsule: U.S. Patent No. 9037807

    • Patent Identification: U.S. Patent No. 9,037,807, "Processor Arrangement on a Chip Including Data Processing, Memory, and Interface Elements," issued May 19, 2015.
    • Technology Synopsis: This patent claims a multi-processor system where data processing elements, memory elements, and interface elements are interconnected by a bus system. The bus system is described as being adapted for dynamically establishing and releasing transmission channels and forming at least one ring that includes pipeline-registers (Compl. ¶¶189-191).
    • Asserted Claims: At least independent claim 1 (Compl. ¶184).
    • Accused Features: Intel's ring bus architecture, which is alleged to dynamically establish connections between cores, LLC slices, and the System Agent, and to form a ring configuration using pipeline registers within its cache boxes (Compl. ¶¶189-191).

  • Multi-Patent Capsule: U.S. Patent No. 9075605

    • Patent Identification: U.S. Patent No. 9,075,605, "Methods and Devices for Treating and Processing Data," issued July 7, 2015.
    • Technology Synopsis: The patent describes a method of operating a multiprocessor system by dynamically adjusting the clock frequency. The frequency is first set to a minimum based on pending operations of a first processor, then increased to a maximum based on pending operations of a second processor, and subsequently reduced based on temperature thresholds and a hysteresis characteristic (Compl. ¶¶211-213).
    • Asserted Claims: At least independent claim 1 (Compl. ¶208).
    • Accused Features: Intel’s Turbo Boost technology, which is alleged to perform a method of adjusting clock frequencies of processors (e.g., graphics and core processors) based on workload, temperature, and power limits (Compl. ¶¶209, 211-213).

  • Multi-Patent Capsule: U.S. Patent No. 9170812

    • Patent Identification: U.S. Patent No. 9,170,812, "Data Processing System Having Integrated Pipelined Array Data Processor," issued October 27, 2015.
    • Technology Synopsis: The patent claims a device with a data processor core and an array data processor (e.g., a graphics processor). These are connected to a shared multi-level cache that has a plurality of cache slices. An instruction dispatch unit, separate from the core, dispatches software threads to the array data processor for parallel execution (Compl. ¶¶233-235).
    • Asserted Claims: At least independent claim 12 (Compl. ¶230).
    • Accused Features: Intel processors with integrated graphics, which allegedly include a media pipeline that dispatches threads to graphics execution units, sharing a multi-level cache (like the LLC) with the main processor cores (Compl. ¶¶231-235).

  • Multi-Patent Capsule: U.S. Patent No. 9250908

    • Patent Identification: U.S. Patent No. 9,250,908, "Multi-Processor Bus and Cache Interconnection System," issued February 2, 2016.
    • Technology Synopsis: The patent describes a system with processors and a separated cache (e.g., LLC). A bus system connects these components and an interface transmits data using a protocol that includes module IDs for the sender and receiver. The separated cache comprises segments for at least some of the processors (Compl. ¶¶255, 258-259).
    • Asserted Claims: At least independent claim 4 (Compl. ¶252).
    • Accused Features: Intel processors where cores, the System Agent, and LLC slices allegedly have module IDs and use a protocol on the ring bus to transmit data between them, with each LLC slice acting as a separate cache segment (Compl. ¶¶256-259).

  • Multi-Patent Capsule: U.S. Patent No. 9436631

    • Patent Identification: U.S. Patent No. 9,436,631, "Chip Including Memory Element Storing Higher Level Memory Data on a Page by Page Basis," issued September 6, 2016.
    • Technology Synopsis: The patent claims a bus system for a multiprocessor system comprising a plurality of bus segments for each processor. The bus provides flexible data channels according to algorithms to be executed in parallel. An identifier is transmitted with the data to identify the source and/or select the target of the data transfer (Compl. ¶¶280-282).
    • Asserted Claims: At least independent claim 1 (Compl. ¶278).
    • Accused Features: Intel's ring bus system, which is alleged to be segmented and provide flexible data channels to each core based on the running algorithm, and to transmit an identifier with data to direct the transfer between a source (e.g., a core) and a target (e.g., an LLC slice) (Compl. ¶¶279-282).

  • Multi-Patent Capsule: U.S. Patent No. 9552047

    • Patent Identification: U.S. Patent No. 9,552,047, "Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply," issued January 24, 2017.
    • Technology Synopsis: This patent describes a multiprocessor system where the clock frequency of at least some data processing units is adjustable at runtime without affecting the clock frequency of other units. The system includes a voltage supply adapted to provide higher voltages for data processing at higher clock frequencies (Compl. ¶¶305-306).
    • Asserted Claims: At least independent claim 1 (Compl. ¶299).
    • Accused Features: Intel's processors with Turbo Boost and integrated voltage regulators, which allegedly allow the clock speed and voltage of certain cores/graphics processors to be adjusted at runtime independently of other units (Compl. ¶¶301, 305-306).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are Intel Core processors (including Core i3, i5, i7, i9), Intel Xeon processors, and Intel Celeron processors that incorporate "Sandy Bridge and above microarchitectures" (Compl. ¶¶32-34). Specific technologies also accused include Intel's Turbo Boost, Turbo Boost Max 3.0, and Foveros 3D stacking (Compl. ¶¶12, 14, 35).

Functionality and Market Context

  • The complaint focuses on the introduction of a "ring bus" architecture with the Sandy Bridge microarchitecture in 2011 (Compl. ¶10). This architecture is alleged to provide a scalable interconnect between multiple processor cores, processor graphics, and a shared Last Level Cache (LLC) (Compl. ¶¶10, 45). The complaint provides a diagram titled "Sandy Bridge: Overview" illustrating the interconnection of cores, LLC, and a System Agent (Compl. p. 4).
  • The complaint also targets Intel's "Turbo Boost" technology, which "accelerates processor and graphics performance for peak loads, automatically allowing processor cores to run faster than the rated operating frequency" (Compl. ¶18). Further, the "Foveros" 3D packaging technology is accused, which involves stacking high-performance logic chiplets (like CPUs) on top of a base die containing I/O and power delivery circuits (Compl. ¶19, 138).
  • The complaint alleges that Intel holds over an 80% market share in computer processor technology and that the business segments responsible for the accused processors generated over $69 billion in revenue in 2018 (Compl. ¶¶3, 11).

IV. Analysis of Infringement Allegations

7,928,763 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of data processing cells, each adapted for sequentially executing at least one of algebraic and logic functions and having at least one arithmetic logic unit; at least one data register file; a program pointer; and at least one instruction decoder The accused processors include a plurality of cores, each containing ALUs, general purpose registers, an instruction pointer, and decoders. A diagram titled "Putting it Together - Core Microarchitecture" illustrates these components (Compl. p. 13). ¶¶40-41 col. 1:21-26
a plurality of memory cells The accused processors include Last Level Caches (LLCs). ¶42 col. 1:27-28
at least one interface unit The accused processors include a System Agent that connects to the LLCs and cores. ¶43 col. 1:29-30
at least one Memory Management Unit (MMU) The accused processors include memory management functionalities. ¶44 col. 1:31-32
a bus system... adapted for programmably interconnecting at runtime at least one of data processing cells and memory cells with at least one of memory cells and one or more of the at least one interface unit. The accused processors include a ring bus system that programmably interconnects the cores (data processing cells), LLCs (memory cells), and the System Agent (interface unit) at runtime. A "Ring Illustration" depicts this interconnection (Compl. p. 15). ¶45 col. 1:33-40
  • Identified Points of Contention (’763 Patent):
    • Scope Questions: A central question may be whether the term "data processing cell" as described in the patent, which includes a program pointer and instruction decoder, reads on a modern processor core that executes out-of-order micro-ops. Further, the construction of "programmably interconnecting at runtime" will be critical, specifically whether it covers the dynamic but structured routing of a ring bus or implies a more flexible, crossbar-like interconnection.
    • Technical Questions: What evidence does the complaint provide that the accused Last Level Caches constitute a "plurality of memory cells" in the manner claimed, as opposed to a single, logically unified cache that is physically distributed?

8,301,872 Patent Infringement Allegations

Claim Element (from Independent Claim 2) Alleged Infringing Functionality Complaint Citation Patent Citation
a cache system including... a first cache level that includes at least one cache and... at least one superior cache level including a plurality of same level cache nodes The accused processors have multiple cache levels, including L1/L2 caches (first cache level) and multiple Last Level Caches (LLCs) which act as same-level cache nodes at a superior level. ¶¶64-66 col. 4:2-8
for each of at least one of the plurality of processor cores, a respective cache of the first cache level is assigned and dedicated to the respective processor core Each processor core includes at least a first level cache (e.g., L1 cache) that is dedicated to that core exclusively. ¶68 col. 4:10-14
the bus system includes segments interconnecting... at least the plurality of same level cache nodes (i) to each other and (ii) to the plurality of processor cores The ring bus includes segments that interconnect the LLCs to each other and also connects the LLCs to the cores. A diagram shows the ring bus connecting cores and LLC slices (Compl. p. 22). ¶69 col. 4:15-20
each of the plurality of same level cache nodes is... capable of (i) relaying data from a first one of the segments to which it is connected to a second one... and (ii) transmitting data between its internal cache memory and the segments Each LLC is connected to at least two segments of the ring bus and is alleged to be capable of relaying data between those segments, as well as transmitting data to and from its own internal memory. The complaint provides a diagram illustrating the connections of an LLC to the bus (Compl. p. 24). ¶72 col. 4:26-34
  • Identified Points of Contention (’872 Patent):
    • Scope Questions: The dispute may turn on the definition of "relaying data." Does this term require the cache node to act as a passive conduit for data destined for another node, or can it be read more broadly to cover the complex cache coherency protocols used in modern ring bus architectures where data is passed between cache slices?
    • Technical Questions: What is the technical mechanism by which an LLC in an Intel processor "relays" data between two segments of the ring bus to which it is attached? The complaint's allegations are conclusory on this point, raising the evidentiary question of how this function is actually performed in the accused devices.

V. Key Claim Terms for Construction

  • The Term: a bus system... adapted for programmably interconnecting at runtime (’763 Patent, Claim 1)
  • Context and Importance: This term is the central limitation describing the connection fabric. The infringement case for the ’763 Patent hinges on whether Intel's ring bus architecture, which has a defined topology, falls under this potentially broad definition. Practitioners may focus on this term because its scope will determine whether the claim is limited to the specific reconfigurable architectures of the patent's era or can be read to cover modern, high-performance interconnects.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification discusses "reconfigurable data processing architectures" in general terms and states that function cells and memory cells "are linked together directly or by one or more bus systems" ('763 Patent, col. 1:35-37), which may support a reading that covers any bus that can alter connections during operation.
    • Evidence for a Narrower Interpretation: The detailed description focuses on "function cell-memory cell combinations" where a function cell directly controls a memory cell to form a "sequencer structure" ('763 Patent, col. 2:21-34, col. 3:19-25). This context may support a narrower interpretation where "programmably interconnecting" requires the specific type of flexible, reconfigurable connections needed to form such dynamic sequencer structures, potentially distinguishing it from a more rigid ring bus topology.
  • The Term: relaying data (’872 Patent, Claim 2)
  • Context and Importance: This term defines a key capability of the "same level cache nodes" (the accused LLCs). The infringement allegation depends on showing that the LLC slices perform this specific function. Intel may argue that its cache coherency protocol involves broadcasting, snooping, and forwarding data packets in a manner technically distinct from simple "relaying," while PACT may argue "relaying" should be given its plain and ordinary meaning, which would cover passing data through.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract states the cache node is capable of "relaying data from a first one of the segments... to a second one," which suggests a general data-forwarding capability without imposing specific technical limitations ('872 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The specification describes data flow in a "cellular structure" and may contain specific embodiments or figures illustrating the "relaying" function in a way that implies a pass-through or routing capability distinct from the complex protocols that govern data movement and ownership states in a modern shared cache. The exact implementation details in the specification could be used to argue for a narrower definition.

VI. Other Allegations

  • Indirect Infringement: For each asserted patent, the complaint alleges both induced and contributory infringement (Compl. ¶¶48-55, 75-82). The allegations state that Intel provides products to OEMs with knowledge they will be incorporated into infringing systems. Inducement is alleged based on Intel's provision of technical documentation, datasheets, and developer manuals that instruct customers on how to use the infringing features (e.g., the ring bus and multi-core cache system) (Compl. ¶¶50, 77). Contributory infringement is alleged on the basis that the accused processors' components are especially made for use in an infringing manner and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶53, 80).
  • Willful Infringement: For each asserted patent, the complaint alleges willful infringement based on Intel’s purported actual knowledge of the patents and its infringement prior to the filing of the current lawsuit (Compl. ¶¶58, 85). This knowledge is alleged to arise, at a minimum, from the service of the complaint in a prior, related lawsuit between the same parties involving the same patents: PACT XPP Schweiz AG v. Intel Corp, 1:19-cv-00267 (DED) (Compl. ¶¶47, 74).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can patent claims drafted in the context of early-2000s reconfigurable computing architectures be construed to cover the specific, highly optimized, and structurally distinct microarchitectures of modern Intel processors? The dispute will likely center on whether terms like "programmably interconnecting" and "relaying data" are broad enough to read on Intel's ring bus and cache coherency protocols.
  • A second key question will be one of technical evidence: assuming a favorable claim construction for the plaintiff, what technical evidence can be presented to prove that the accused products operate in the precise manner claimed? For example, the complaint's allegation that Intel's LLCs perform a "relaying" function as claimed in the ’872 patent will require detailed technical evidence that goes beyond high-level block diagrams and establishes a functional match at the operational level.
  • The litigation's financial stakes are significantly heightened by the question of willful infringement. The complaint's reliance on a prior lawsuit to establish pre-suit knowledge creates a central issue for any potential damages calculation, raising the possibility of enhancement should infringement be found.