DCT
1:19-cv-01573
GlobalFoundries US Inc v. Xilinx
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Globalfoundries U.S. Inc. (Delaware)
- Defendant: Xilinx, Inc. (Delaware) and Mouser Electronics, Inc. (Delaware)
- Plaintiff’s Counsel: Farnan LLP
- Case Identification: 1:19-cv-01573, D. Del., 08/26/2019
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because both Defendants are incorporated in Delaware and thus reside in the district.
- Core Dispute: Plaintiff alleges that Defendants' field-programmable gate arrays (FPGAs) and other advanced integrated circuits, manufactured by a third-party foundry (TSMC), infringe three patents related to FinFET semiconductor device structures and manufacturing methods.
- Technical Context: The lawsuit concerns foundational technologies for manufacturing high-performance, sub-30nm semiconductors, a field characterized by intense competition and substantial R&D investment.
- Key Procedural History: The complaint notes that Plaintiff Globalfoundries acquired IBM's microelectronics business in 2015, including a portfolio of 16,000 patents and applications, from which the asserted ’418 patent originated.
Case Timeline
| Date | Event |
|---|---|
| 2006-01-20 | ’418 Patent Priority Date |
| 2009-10-09 | ’603 Patent Priority Date |
| 2010-07-06 | ’418 Patent Issue Date |
| 2013-03-12 | ’986 Patent Priority Date |
| 2014-12-16 | ’603 Patent Issue Date |
| 2015-01-20 | ’986 Patent Issue Date |
| 2015-01-01 | Globalfoundries completes acquisition of IBM Microelectronics Business |
| 2019-08-26 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,912,603 - "Semiconductor device with stressed fin sections"
The Invention Explained
- Problem Addressed: The patent's background section describes the difficulty of applying conventional channel straining techniques to three-dimensional FinFET transistors, noting that traditional methods are less effective and that device scaling reduces the available space for depositing stress-inducing materials (ʼ603 Patent, col. 3:1-44).
- The Patented Solution: The invention proposes a method to create more effective strain. It involves first forming the FinFET gate structures, then selectively etching away the exposed portions of the semiconductor fin between the gates to create gaps. These gaps are then filled with a "stress/strain inducing material" (e.g., silicon germanium), which creates well-defined stressor regions that are self-aligned to the gates and can more efficiently impart stress to the transistor channel to improve performance (ʼ603 Patent, Abstract; col. 8:5-32).
- Technical Importance: This approach provides a targeted and structurally integrated way to boost transistor performance in advanced FinFETs, a critical factor for continuing semiconductor scaling.
Key Claims at a Glance
- The complaint asserts independent claim 15 (Compl. ¶23).
- The essential elements of claim 15 are:
- A semiconductor device comprising: a semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments, wherein each upper surface segment ends at a respective first end sidewall and a respective second end side wall, and wherein each gap is bounded in the first direction by a selected first end sidewall and an adjacent second end sidewall; and
- a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. 7,750,418 - "Introduction of metal impurity to change workfunction of conductive electrodes"
The Invention Explained
- Problem Addressed: The patent identifies a problem in advanced transistors that use high-k dielectrics as the gate insulator. With these materials, it can be difficult to achieve the ideal threshold voltage for turning the transistor on, particularly for n-type MOSFETs, which can negatively impact device performance (ʼ418 Patent, col. 1:46-59).
- The Patented Solution: The patent describes a method to tune the workfunction of the gate stack. This is achieved by introducing specific "workfunction altering metal impurities" into a metal-containing layer (such as titanium nitride) that sits above the high-k dielectric. The choice of impurity allows for adjusting the workfunction to set the desired threshold voltage for both n-type and p-type transistors (ʼ418 Patent, Abstract; col. 2:21-30).
- Technical Importance: This technology gives fabricators a critical tool for controlling transistor characteristics in high-k metal gate (HKMG) processes, enabling the creation of complex, high-performance CMOS circuits.
Key Claims at a Glance
- The complaint asserts independent claim 27 (Compl. ¶36).
- The essential elements of claim 27 are:
- A method of changing workfunction of a conductive stack comprising: providing a material stack that comprises a dielectric having a dielectric constant of greater than silicon dioxide, a metal-containing material located above said dielectric, and a conductive electrode located directly on an upper surface of said metal-containing material; and
- introducing at least one workfunction altering metal impurity into said metal-containing material wherein said at least one workfunction altering metal impurity is introduced during forming of a metal impurity containing layer or after formation of a layer containing said metal-containing material.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. 8,936,986 - "Methods of forming finfet devices with a shared gate structure"
The Invention Explained
The patent addresses manufacturing complexities in FinFET devices where N-type and P-type transistors are built adjacent to each other and share a common gate. The invention discloses a method for forming a sidewall spacer around the entire perimeter of a shared sacrificial gate structure through a "single deposition process operation and a single etching process operation," which is intended to simplify the fabrication flow (ʼ986 Patent, Abstract; col. 2:16-24).
Key Claims at a Glance
The complaint asserts independent claim 1 (Compl. ¶50).
Accused Features
The complaint alleges that the process used by TSMC to manufacture the accused products includes forming a gate over both NMOS and PMOS fins and then forming a sidewall spacer around the gate structure, which is alleged to involve single deposition and etch processes (Compl. ¶¶ 54-55).
III. The Accused Instrumentality
Product Identification
The accused products are Xilinx's integrated circuits, including field programmable gate arrays (FPGAs), adaptive compute acceleration platforms (ACAPs), systems on a chip (SoCs), and specifically names the Xilinx XCKU3P and XCKU15P families of FPGAs and other Kintex UltraScale+ FPGAs (Compl. ¶¶ 23, 36, 50).
Functionality and Market Context
These products are advanced, programmable semiconductor devices. The complaint alleges they are manufactured by Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) using its 28 nanometer, 16 nanometer, and smaller process technologies (Compl. ¶6, fn. 1). The infringement allegations focus on the physical structure and manufacturing methods of the silicon chips themselves, rather than their end-use software or programmable functions. The complaint notes that Xilinx generated more net revenue from the United States than any other country in 2016, 2017, and 2018 (Compl. ¶¶ 30, 43, 58).
IV. Analysis of Infringement Allegations
U.S. Patent No. 8,912,603 Infringement Allegations
| Claim Element (from Independent Claim 15) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments... | The accused products are integrated circuits fabricated with a process that includes fins with an upper surface that is interrupted by gaps, forming discontinuous segments. | ¶27 | col. 10:1-11 |
| a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall. | The accused products are fabricated using a process where a SiGe (silicon germanium) epitaxial layer is used for embedded strain technology that at least partially fills the gaps. | ¶28 | col. 10:18-24 |
Identified Points of Contention
- Technical Questions: A key factual question will be whether the structures in TSMC's process, as used in the accused products, meet the claim limitations. This will likely depend on evidence from reverse engineering and analysis of TSMC's confidential process specifications. The complaint's specific identification of a "SiGe epitaxial layer" suggests Plaintiff believes it has evidence on this point.
- Scope Questions: The term "discontinuous upper surface segments" may become a point of claim construction. The dispute could center on whether a partial recess in the fin is sufficient to render the segments "discontinuous," or if a more complete separation is required by the patent's specification and prosecution history.
U.S. Patent No. 7,750,418 Infringement Allegations
| Claim Element (from Independent Claim 27) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| providing a material stack that comprises a dielectric having a dielectric constant of greater than silicon dioxide, a metal-containing material located above said dielectric, and a conductive electrode located directly on an upper surface of said metal-containing material | The manufacturing process for the accused products allegedly creates a material stack for p-type FETs comprising HfO (a high-k dielectric), interfacial TiN (a metal-containing material), and TiN WF (a conductive electrode). | ¶40 | col. 7:42-49 |
| introducing at least one workfunction altering metal impurity into said metal-containing material wherein said at least one workfunction altering metal impurity is introduced... after formation of a layer containing said metal-containing material. | The manufacturing process allegedly includes introducing a "TiAlCOClf fill" into the metal-containing material. The complaint alleges this fill constitutes at least one workfunction altering metal impurity introduced after formation of the metal-containing layer. | ¶41 | col. 7:50-58 |
Identified Points of Contention
- Technical Questions: The infringement allegation hinges on the specific nature of the "TiAlCOClf fill" used in TSMC's process. A central dispute will be whether this material functions as a "workfunction altering metal impurity" that is introduced into the TiN layer, or if it is a distinct layer with a different primary purpose. This is a highly technical question requiring detailed evidence of the manufacturing process.
- Scope Questions: The claim requires "introducing" an "impurity." A defendant may argue that forming a distinct layer of "TiAlCOClf" is not "introducing" an "impurity" as those terms are used in the patent, raising a significant claim construction issue.
No probative visual evidence provided in complaint.
V. Key Claim Terms for Construction
For the ’603 Patent
- The Term: "discontinuous upper surface segments"
- Context and Importance: This term is the core of the claimed structure. Its construction will determine whether the fin structures within the accused products, which the complaint alleges have an "interrupted" upper surface, meet the claim limitation. Practitioners may focus on this term because the degree of "interruption" required to create "discontinuous" segments is not explicitly quantified.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language itself focuses on the "upper surface" being "interrupted by gaps." Plaintiff may argue that any structurally significant gap that breaks the continuous plane of the fin's top surface is sufficient, without requiring a complete severing of the fin body underneath.
- Evidence for a Narrower Interpretation: The patent's figures, such as Figure 15 showing gap 164, depict a complete removal of fin material between gate structures, creating physically separate fin sections. A defendant could argue these embodiments limit the term to require fully separated segments, not merely recessed or thinned portions.
For the ’418 Patent
- The Term: "workfunction altering metal impurity"
- Context and Importance: The infringement theory rests entirely on whether the "TiAlCOClf fill" alleged to be used in the accused products constitutes such an "impurity." The definition will be dispositive for this patent. Practitioners may focus on this term because it combines a functional requirement ("workfunction altering") with a structural one ("metal impurity").
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification provides numerous examples of elements that can serve as metal impurities for both n-type and p-type workfunction shifts, suggesting the term is meant to be exemplary, not exhaustive (ʼ418 Patent, col. 6:30-56). Plaintiff will likely argue that any metallic substance introduced to the stack that achieves the claimed function falls within the scope.
- Evidence for a Narrower Interpretation: The term "impurity" often implies a substance introduced in small quantities, like a dopant, rather than a distinct bulk layer. A defendant may argue that the "TiAlCOClf fill" is a primary structural layer, not an "impurity" introduced into the "metal-containing material" (TiN) as required by the claim.
VI. Other Allegations
Indirect Infringement
The complaint alleges that Defendant Xilinx induces infringement by actively encouraging the importation, use, and sale of the accused products. This encouragement is allegedly done through marketing materials, technical specifications, data sheets, websites, user manuals, and sales and support activities (Compl. ¶¶ 29, 43, 57).
Willful Infringement
The complaint asserts that Defendants had knowledge of the asserted patents and their infringement at least as of the date the complaint was filed and served, August 26, 2019. This forms the basis for a claim of post-suit willful infringement (Compl. ¶¶ 30, 44, 58). There are no allegations of pre-suit knowledge.
VII. Analyst’s Conclusion: Key Questions for the Case
This case presents a dispute between major semiconductor industry players over foundational manufacturing technologies. The outcome will likely depend on the answers to a few central questions:
- A primary issue will be one of evidentiary proof: can Globalfoundries obtain and present sufficient evidence from TSMC's highly confidential manufacturing processes to prove that the structures and methods used to create Xilinx’s chips practice the specific steps and result in the final structures required by the asserted claims? The complaint's specific allegations regarding materials like "SiGe" and "TiAlCOClf fill" suggest a belief that such evidence exists.
- A second core issue will be one of definitional scope: will claim construction favor a broader or narrower reading of key terms? The meaning of "discontinuous upper surface segments" ('603 patent) and "workfunction altering metal impurity" ('418 patent) will be critical in determining whether the technical realities of TSMC's process fall within the boundaries of Globalfoundries' patent rights.
- A third question concerns the method vs. product distinction: infringement allegations for the '418 and '986 patents are directed at the manufacturing method. These claims are asserted under 35 U.S.C. § 271(g), which requires showing that the accused products were "made by" the patented process and were not "materially changed by subsequent processes." This may introduce additional layers of technical and legal argument beyond a direct comparison of the final product to the claims.