GlobalFoundries US Inc v. Motorola Mobility LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Globalfoundries U.S. Inc. (Delaware)
  • Defendant: Motorola Mobility LLC (Delaware)
  • Plaintiff’s Counsel: Farnan LLP
• Case Identification: 1:19-cv-01574, D. Del., 08/26/2019
• Venue Allegations: Venue is asserted on the basis that Defendant Motorola Mobility LLC is a Delaware corporation and therefore resides in the district.
• Core Dispute: Plaintiff alleges that Defendant’s mobile device products, which incorporate semiconductor chips manufactured by a third party (TSMC), infringe a patent related to the local interconnect structures within those chips.
• Technical Context: The technology concerns methods for creating electrical connections between transistors on a semiconductor chip, a fundamental challenge in designing and manufacturing smaller, more densely packed integrated circuits.
• Key Procedural History: The complaint notes that Plaintiff Globalfoundries acquired IBM's microelectronics business in 2015, including a portfolio of 16,000 patents and applications, which may provide context for the origin of the asserted intellectual property. No prior litigation or post-grant proceedings involving the asserted patent are mentioned.

Case Timeline

Date	Event
2011-12-13	’910 Patent Priority Date (Application Filing)
2016-05-31	U.S. Patent No. 9,355,910 Issues
2019-08-26	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,355,910 - “Semiconductor device with transistor local interconnects,” issued May 31, 2016

The Invention Explained

• Problem Addressed: The patent describes a challenge in semiconductor manufacturing, particularly at advanced nodes (e.g., 20 nm), where shrinking device dimensions makes it difficult to scale standard cell library logic devices. Traditional methods of "cross-coupling" transistors, which are critical for scaling, rely on standard metal layers that consume significant and undesirable chip area (ʼ910 Patent, col. 1:11-28).
• The Patented Solution: The invention proposes forming local interconnects between transistors at a level below the standard metal layers to conserve space. It describes using dedicated "local interconnect" layers, designated as "CA" and "CB" layers, to create specific connection geometries between the gates of different transistors, such as the "zig-zag or generally S-shape" structure depicted in Figure 8 of the patent (ʼ910 Patent, col. 5:47-68, Fig. 8). This allows for more compact chip designs compared to using the upper-level metal routing layers for such connections (ʼ910 Patent, col. 4:58-65).
• Technical Importance: This approach addresses the need for increased transistor density, a key driver of improved performance and efficiency in modern integrated circuits, by providing a more area-efficient method for creating necessary connections within logic cells (ʼ910 Patent, col. 1:24-28).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 (Compl. ¶16, ¶18).
• The essential elements of independent claim 1 include:
  • A semiconductor substrate with a first and second transistor, each having a source, drain, and gate.
  • A first "CB layer" connected to the gate of the first transistor and a second "CB layer" connected to the gate of the second transistor.
  • A "CA layer" that extends between and electrically connects the first and second CB layers.
  • A specific geometric arrangement where the transistor gates extend along parallel lines, and the CA layer extends generally parallel to these lines and generally perpendicular to the CB layers.
  • A requirement that at least one of the CB layers extends longitudinally beyond the gate of its respective transistor.
• The complaint does not explicitly reserve the right to assert dependent claims but incorporates all preceding paragraphs by reference, which includes a general statement that each element of "at least one claim" is present (Compl. ¶14-15).

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused products as integrated circuits manufactured by Taiwan Semiconductor Manufacturing Company Ltd. ("TSMC") using its "7 Nanometer technology," and products containing these circuits (Compl. ¶16). A specific example provided is the "Motorola 5G Moto Mod that incorporates Qualcomm's Snapdragon 855 system on a chip ('SoC')" (Compl. ¶16). The allegations also extend more broadly to TSMC's "28 nanometer and smaller technology" (Compl. ¶5).

Functionality and Market Context

The complaint alleges that the accused integrated circuits are "semiconductor devices" that contain "standard cells made up of multiple transistors" (Compl. ¶19, ¶23). The functionality at issue is the physical structure and layout of these transistors and their local interconnects, which are alleged to be fabricated using TSMC's 7 Nanometer process (Compl. ¶19-22). The complaint asserts these infringing components are incorporated into Motorola products that are imported, sold, and offered for sale in the United States (Compl. ¶17).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

'910 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a semiconductor substrate;	The accused integrated circuits are fabricated on a semiconductor substrate as part of TSMC's 7 Nanometer process.	¶20	col. 2:41-42
a first transistor and a second transistor disposed on said substrate; each of said transistors comprising a source, a drain, and a gate;	The accused integrated circuits are alleged to contain at least two transistors formed on the substrate, each having a source, a drain, and a gate.	¶21, ¶22	col. 2:44-48
a first CB layer electrically connected to said gate of said first transistor;	The standard cells in the accused products are allegedly fabricated with a "local interconnect layer" that electrically connects to the gate of a first transistor.	¶23	col. 5:47-50
a second CB layer electrically connected to said gate of said second transistor;	The standard cells are allegedly fabricated with "another local interconnect layer" that electrically connects to the gate of a second transistor.	¶24	col. 5:50-52
a CA layer extending longitudinally between a first end and a second end; wherein said first CB layer is electrically connected to said first end of said CA layer; said second CB layer is electrically connected to said second end of said CA layer;	The standard cells are allegedly fabricated with a layer that extends longitudinally to electrically connect the first and second local interconnect layers.	¶25	col. 5:52-56
said gate of said first transistor extends longitudinally along a first line and said gate of said second transistor extends longitudinally along a second line, wherein said first and second lines are generally parallel to one another and spaced apart from one another;	The standard cells allegedly include first and second transistor gates that extend along lines that are generally parallel and spaced apart.	¶26	col. 5:57-61
and said CA layer extends generally parallel to said lines and generally perpendicular to said first CB layer and said second CB layer;	The accused interconnect layer is alleged to be parallel to the lines of the transistor gates and perpendicular to the first and second local interconnect layers it connects.	¶27	col. 5:61-65
and wherein said first CB layer extends longitudinally beyond said gate of said first transistor and/or said second CB layer extends longitudinally beyond said gate of said second transistor.	The local interconnect layers are alleged to be fabricated such that they extend longitudinally beyond the gates of the first and/or second transistors.	¶28	col. 5:47-56

• Identified Points of Contention:
  • Technical Questions: A primary question will be evidentiary: does the physical layout of TSMC's 7nm standard cells, as found in the accused Qualcomm Snapdragon 855 chip, actually contain the specific S-shaped interconnect structure defined by the geometric limitations of claim 1? The complaint's allegations are conclusory, stating that "standard cells are fabricated" with these features, but does not provide visual or documentary evidence of this structure (Compl. ¶23-28).
  • Scope Questions: The case may raise the question of whether the terms "CA layer" and "CB layer," which are specific to the patent, read on the actual structures used in TSMC's manufacturing process. The infringement allegation hinges on mapping these patent-specific terms onto what the complaint calls "local interconnect layer[s]" in the accused products (Compl. ¶23, ¶25).

V. Key Claim Terms for Construction

• The Term: "CA layer" / "CB layer"

  • Context and Importance: These terms are not standard industry nomenclature and are defined within the patent. Their construction will be dispositive for infringement, as Plaintiff must prove that structures within the accused TSMC chips meet the definitions of a "CA layer" and a "CB layer" as claimed. Practitioners may focus on whether these terms are limited to the specific embodiments shown or can encompass any "local interconnect layer" performing a similar function.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification introduces these as a "first local interconnect layer 34" and a "second local interconnect layer 36" (ʼ910 Patent, col. 3:44-46). This could support an argument that the terms encompass a general class of local interconnects, not just a specific structure.
    • Evidence for a Narrower Interpretation: The detailed description and figures repeatedly show these layers in very specific configurations, such as the "long 'T' shape" or the "zig-zag or generally S-shape" (ʼ910 Patent, col. 4:54, col. 5:67-68, Figs. 4, 8). This could support a narrower construction limited to the disclosed structures and their geometric relationships.

• The Term: "generally parallel" / "generally perpendicular"

  • Context and Importance: These terms appear in claim 1 to define the orientation of the CA layer relative to the transistor gates and the CB layers. The scope of "generally" will be critical, as it determines the degree of deviation from perfect parallelism or perpendicularity allowed while still falling within the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The use of the modifier "generally" itself suggests the patentee intended to claim some tolerance and not require strict 90-degree or 180-degree angles, which can be difficult to achieve perfectly in semiconductor fabrication.
    • Evidence for a Narrower Interpretation: The patent figures, such as Figure 8, depict these relationships as being very close to perfectly parallel and perpendicular. A defendant could argue that "generally" only covers minor, unintentional manufacturing variations from the depicted orthogonal layout.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain specific counts or factual allegations for indirect infringement (inducement or contributory infringement). The allegations focus on Defendant's direct infringement through acts of importing, using, and selling the accused products (Compl. ¶16-17).
• Willful Infringement: The complaint does not explicitly allege willful infringement. However, the prayer for relief requests attorneys' fees on the basis that this is an "exceptional case pursuant to 35 U.S.C. § 285," which is an allegation often associated with a finding of willfulness or other litigation misconduct (Compl., Prayer for Relief ¶(f)). The complaint does not plead a factual basis, such as pre-suit knowledge of the patent, to support this request.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this dispute will likely depend on the answers to two central questions:

1. A core issue will be one of claim construction and scope: How broadly will the court construe the patent-specific terms "CA layer" and "CB layer"? Will they be defined functionally as any local interconnects that connect transistor gates in a certain sequence, or will they be limited structurally to the specific "T-shape" and "S-shape" geometries disclosed in the patent's embodiments?

2. A key evidentiary question will be one of technical mapping: Assuming a claim construction, what does a reverse engineering analysis of the accused Qualcomm Snapdragon 855 chip (manufactured with TSMC's 7nm process) actually reveal? Can Globalfoundries produce evidence demonstrating that the physical structures within that chip meet every geometric and connectivity limitation recited in claim 1, including the precise parallel and perpendicular orientations and the requirement that a CB layer "extends longitudinally beyond" a gate?