DCT

1:19-cv-01576

GlobalFoundries US Inc v. Xilinx Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-01576, D. Del., 08/26/2019
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because both Defendants are Delaware corporations and therefore reside in the district.
  • Core Dispute: Plaintiff alleges that Defendants’ field programmable gate arrays (FPGAs) and other advanced integrated circuits, manufactured by a third-party foundry (TSMC), infringe six patents related to semiconductor device structures and manufacturing processes.
  • Technical Context: The dispute centers on foundational technologies for fabricating advanced semiconductor devices at small process nodes (e.g., 28nm and 16nm), affecting the physical layout, material composition, and manufacturing methods of high-performance chips.
  • Key Procedural History: Plaintiff Globalfoundries states it acquired a portfolio of 16,000 IBM patents in 2015, including two of the asserted patents ('497 and '966). The complaint alleges that Defendants had knowledge of their infringement of the asserted patents as of the filing date of this action.

Case Timeline

Date Event
2002-04-16 '167 Patent Priority Date
2003-02-11 '167 Patent Issue Date
2006-01-20 '497 Patent Priority Date
2008-09-16 '497 Patent Issue Date
2009-09-03 '966 Patent Priority Date
2011-10-18 '966 Patent Issue Date
2011-12-13 '348 and '910 Patents Priority Date
2012-01-16 '633 Patent Priority Date
2013-11-12 '348 Patent Issue Date
2013-12-03 '633 Patent Issue Date
2015-01-01 Globalfoundries acquires IBM patent portfolio (approx. date)
2016-05-31 '910 Patent Issue Date
2019-08-26 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,581,348 - “Semiconductor device with transistor local interconnects,” Issued November 12, 2013

The Invention Explained

  • Problem Addressed: As semiconductor device features shrink, particularly at the 20nm node and below, creating compact standard cell library devices (like scan-D flip-flops) becomes difficult due to lithographic limitations. Traditional methods of "cross-coupling" transistors using standard metal layers consume excessive and undesirable device area ('348 Patent, col. 1:10-25).
  • The Patented Solution: The patent describes a semiconductor device structure that uses special "local interconnect" layers, designated "CA" and "CB" layers, to connect different components of transistors (sources, drains, gates) to each other. These local interconnects are situated below the standard metal layers and closer to the transistors, allowing for more area-efficient cross-coupling ('348 Patent, Abstract; col. 3:22-38).
  • Technical Importance: This approach allows for the creation of smaller, more densely packed standard cell logic devices, which is a critical factor in the continued scaling and performance improvement of integrated circuits ('348 Patent, col. 1:18-25).

Key Claims at a Glance

  • The complaint asserts independent claim 1 ('Compl. ¶26).
  • The essential elements of independent claim 1 include:
    • A semiconductor substrate.
    • A first transistor and a second transistor on the substrate, each with a source, drain, and gate.
    • A "CA layer" electrically connected to at least one of the source or drain of the first transistor.
    • A "CB layer" electrically connected to both gates of the transistors and to the CA layer.
  • The complaint reserves the right to assert other claims ('Compl. ¶26).

U.S. Patent No. 9,355,910 - “Semiconductor device with transistor local interconnects,” Issued May 31, 2016

The Invention Explained

  • Problem Addressed: Similar to the '348 patent, this invention addresses the challenge of scaling standard cell library devices by avoiding the use of area-intensive standard metal layers for cross-coupling transistors ('910 Patent, col. 1:11-26).
  • The Patented Solution: The patent discloses a specific geometric arrangement for local interconnects. The gates of two transistors are formed as parallel lines. A "CA layer" also extends parallel to these gate lines, while two "CB layers" connect the gates to the CA layer in a perpendicular fashion. This creates a structured, S-shaped, or zig-zag interconnect path between the transistors ('910 Patent, Abstract; col. 5:48-62).
  • Technical Importance: This highly defined geometric layout provides a predictable and space-efficient method for achieving dense transistor cross-coupling, a key requirement for advanced logic cells ('910 Patent, col. 1:19-26).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶42).
  • The essential elements of independent claim 1 include:
    • A semiconductor substrate with a first and second transistor.
    • A first CB layer connected to the gate of the first transistor and a second CB layer connected to the gate of the second transistor.
    • A CA layer connecting the first and second CB layers.
    • A specific geometric arrangement where the transistor gates extend along parallel lines, the CA layer also extends parallel to those lines, and the CA layer is perpendicular to the first and second CB layers.
    • At least one CB layer extends longitudinally beyond the gate of its respective transistor.
  • The complaint reserves the right to assert other claims (Compl. ¶42).

Multi-Patent Capsule: U.S. Patent No. 7,425,497

  • Patent Identification: U.S. Patent No. 7,425,497, "Introduction of metal impurity to change workfunction of conductive electrodes," Issued September 16, 2008.
  • Technology Synopsis: The patent describes a method for fabricating transistors with high-k dielectrics. The method adjusts the transistor's threshold voltage by introducing specific "workfunction altering metal impurities" (e.g., lanthanide series elements for n-type, or Group VIB-VIII elements for p-type) into a metal-containing layer (e.g., TiN) in the gate stack ('497 Patent, Abstract).
  • Asserted Claims: Claim 1 is asserted as a method claim (Compl. ¶62).
  • Accused Features: The complaint alleges that the process used by TSMC to manufacture the accused products infringes by providing a stack with an Hf-based dielectric, a titanium-containing material, and introducing tantalum (a Group VB metal) to alter the workfunction for n-type FETs (Compl. ¶¶66-67).

Multi-Patent Capsule: U.S. Patent No. 8,598,633

  • Patent Identification: U.S. Patent No. 8,598,633, "Semiconductor device having contact layer providing electrical connections," Issued December 3, 2013.
  • Technology Synopsis: This patent discloses a specific structure for routing power to transistors. It describes a "contact layer" situated below a metal power rail, which has a first portion outside the transistor's diffusion region (connecting to the power rail via a via) and a second portion that extends into the diffusion region to connect directly to the transistor ('633 Patent, Abstract).
  • Asserted Claims: Claim 1 is asserted as a device claim (Compl. ¶76).
  • Accused Features: The accused products are alleged to contain a contact layer (formed below the M1 metal level) that connects a transistor within a diffusion region to an external power rail in the manner claimed (Compl. ¶¶82-84).

Multi-Patent Capsule: U.S. Patent No. 6,518,167

  • Patent Identification: U.S. Patent No. 6,518,167, "Method of forming a metal or metal nitride interface layer between silicon nitride and copper," Issued February 11, 2003.
  • Technology Synopsis: The patent details a method to improve the adhesion between a copper interconnect layer and the silicon nitride capping layer above it, which is critical for preventing delamination and improving reliability. The method involves providing a metal organic gas over the copper to form a thin metal or metal nitride interface layer before the silicon nitride is deposited ('167 Patent, Abstract).
  • Asserted Claims: Claim 1 is asserted as a method claim (Compl. ¶92).
  • Accused Features: The complaint alleges that TSMC's manufacturing process infringes by using a selective Chemical Vapor Deposition (CVD) cobalt process to form a metal interface layer between copper and silicon nitride layers (Compl. ¶¶95-99).

Multi-Patent Capsule: U.S. Patent No. 8,039,966

  • Patent Identification: U.S. Patent No. 8,039,966, "Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects," Issued October 18, 2011.
  • Technology Synopsis: This patent describes a structure for capping copper wires to improve electromigration resistance. The structure includes a metal cap (e.g., cobalt) on the copper core, followed by a dielectric cap. A critical aspect is that the interface between the copper and the metal cap is formed "in-situ" without exposure to oxygen, preventing the formation of an oxide layer that weakens the interface ('966 Patent, Abstract).
  • Asserted Claims: Claim 12 is asserted as a structure claim (Compl. ¶108).
  • Accused Features: The accused products are alleged to have interconnects with a copper core, a cobalt metal cap, and a subsequent dielectric cap, where the interface between the copper and cobalt cap is oxygen-free (Compl. ¶¶113, 115, 117).

III. The Accused Instrumentality

  • Product Identification: The accused products are identified as Xilinx's field programmable gate arrays (FPGAs), including 3D ICs, adaptive compute acceleration platforms (ACAPs), and systems on a chip (SoCs). Specific product families named include the Xilinx XCKU3P, XCKU15P, and other Kintex UltraScale+ FPGAs (Compl. ¶¶10, 26, 42).
  • Functionality and Market Context: The complaint alleges these products are advanced integrated circuits manufactured for Xilinx by Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) using TSMC's 28 nanometer, 16 nanometer, and smaller process technologies (Compl. ¶¶6, 26). The infringement allegations focus on the fundamental structures and manufacturing processes of the chips themselves, rather than their end-use functions. The complaint positions Xilinx as a major semiconductor company with significant U.S. sales, and Mouser as a key distributor of these products (Compl. ¶¶35, 38).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

'348 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a semiconductor device comprising: a semiconductor substrate; The accused products are integrated circuits fabricated on a semiconductor substrate using TSMC's 16nm process. ¶29, ¶30 col. 2:40-41
a first transistor and a second transistor formed on said semiconductor substrate; each of said transistors comprising a source, a drain, and a gate; The accused products are integrated circuits containing at least two transistors, each with a source, drain, and gate. ¶31, ¶32 col. 2:42-45
a CA layer electrically connected to at least one of said source or said drain of said first transistor; The accused products allegedly include SRAM cells fabricated with a local interconnect layer that electrically connects to the source or drain of a first transistor. ¶33 col. 3:25-27
and a CB layer electrically connected to both of said gates of said transistors and said CA layer. The accused products allegedly include SRAM cells fabricated with a local interconnect layer that electrically connects the gates of the first and second transistors and another local interconnect layer. ¶34 col. 3:27-30

'910 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a semiconductor device comprising: a semiconductor substrate; a first transistor and a second transistor disposed on said substrate; each of said transistors comprising a source, a drain, and a gate; The accused products are integrated circuits fabricated on a semiconductor substrate and contain at least two transistors, each with a source, drain, and gate. ¶45-¶48 col. 2:40-45
a first CB layer electrically connected to said gate of said first transistor; a second CB layer electrically connected to said gate of said second transistor; The accused SRAM cells are allegedly fabricated with separate local interconnect layers that electrically connect to the gates of a first and second transistor, respectively. ¶49, ¶50 col. 4:50-54
and a CA layer extending longitudinally between a first end and a second end; wherein said first CB layer is electrically connected to said first end of said CA layer; said second CB layer is electrically connected to said second end of said CA layer; The accused SRAM cells are allegedly fabricated with a layer that extends longitudinally to electrically connect the first and second local interconnect layers. ¶51 col. 4:45-49
said gate of said first transistor extends longitudinally along a first line and said gate of said second transistor extends longitudinally along a second line, wherein said first and second lines are generally parallel to one another... The accused SRAM cells allegedly have first and second transistors with gates that extend along lines that are generally parallel to one another. ¶52 col. 5:48-52
and said CA layer extends generally parallel to said lines and generally perpendicular to said first CB layer and said second CB layer; The accused SRAM cells are allegedly fabricated such that a local interconnect layer is parallel to the gate lines and perpendicular to the first and second local interconnect layers connected to the gates. ¶53 col. 5:53-56
and wherein said first CB layer extends longitudinally beyond said gate of said first transistor and/or said second CB layer extends longitudinally beyond said gate of said second transistor. The local interconnect layers connected to the gates allegedly extend longitudinally beyond the gates of the first and/or second transistor. ¶54 col. 5:57-62

Identified Points of Contention

  • Evidentiary Questions: The complaint's allegations for both the '348 and '910 patents rely on the structure of "SRAM cells" within the accused products. A primary point of contention will be the factual evidence supporting these claims. The complaint does not provide specific evidence (like circuit diagrams or microscopy) of the accused structures, raising the question of what discovery will reveal about the actual layout of these cells.
  • Scope Questions: For the '348 patent, a key question is whether the accused "local interconnect layer" meets the functional requirements of being a "CA layer" and a "CB layer" as defined by the patent. For the '910 patent, the geometric limitations are highly specific ("generally parallel," "generally perpendicular"). A central question will be whether the accused SRAM cell layouts meet these precise geometric constraints, or if there is a technical mismatch. The use of "generally" in the claim may become a focus of the claim construction dispute.

V. Key Claim Terms for Construction

  • The Term: "CA layer" / "CB layer" (from '348 Patent, Claim 1; '910 Patent, Claim 1)
  • Context and Importance: These terms appear to be coined by the patentee and are not standard industry terms. Their construction is critical because the infringement allegations map them directly onto a "local interconnect layer" allegedly found in the accused products' SRAM cells (Compl. ¶¶33-34, 49-51). The outcome of the case for the '348 and '910 patents may depend entirely on whether the accused structures fall within the court's definition of these terms.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification repeatedly refers to these as "local interconnect" layers, which could support an argument that they encompass any local wiring layer used for cross-coupling below the main metal layers ('348 Patent, col. 3:22-24). The specification also states they can be formed of common materials like tungsten or copper, suggesting they are not exotic structures ('348 Patent, col. 3:32-38).
    • Evidence for a Narrower Interpretation: The claims themselves impose specific connectivity requirements. For example, '348 claim 1 requires the CB layer to connect to both transistor gates and the CA layer, which itself connects to a source/drain. The detailed figures (e.g., '348 Patent, FIG. 4; '910 Patent, FIG. 8) depict very specific T-shaped and L-shaped layouts, which a defendant might argue limit the scope of the terms to those specific embodiments. The '910 patent further constrains the terms with explicit geometric relationships (e.g., parallel and perpendicular).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for all asserted patents. The factual basis alleged is that Xilinx actively promotes the importation, sale, and use of the accused products through marketing materials, technical specifications, data sheets, user manuals, and customer support, thereby encouraging infringement by its customers and distributors (e.g., Compl. ¶¶35, 55, 69, 85, 101, 119).
  • Willful Infringement: The complaint does not explicitly allege willful infringement. However, for each patent, it alleges that the filing of the complaint and the sending of a letter on August 26, 2019, provided Xilinx with knowledge of the patents and their infringement. This lays the groundwork for a claim of post-suit willful infringement (e.g., Compl. ¶¶36, 56, 70, 86, 102, 120).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. An Evidentiary Question of Process: A significant portion of the infringement case, especially for the method patents ('497, '167) and the in-situ formation claims of the '966 patent, relies on the specific, non-public manufacturing processes used by TSMC in a foreign foundry. A central question for the litigation will be: what evidence can Globalfoundries obtain through discovery and present to prove that TSMC's proprietary processes map onto the specific steps and conditions recited in the claims?

  2. A Definitional Question of Structure: For the device patents ('348, '910, '633, '966), the claims recite specific structures with patentee-defined terms (e.g., "CA layer," "CB layer") and precise material compositions and arrangements (e.g., an oxygen-free interface between a copper core and a cobalt cap). A core issue will be one of claim scope and technical equivalence: will the physical structures within the accused Xilinx chips, as revealed through reverse engineering and discovery, be found to meet the exact definitions and arrangements required by the claims, or will subtle but material differences in layout, geometry, or materials place them outside the scope of the patents?

  3. A Jurisdictional Question of Importation: For the method claims asserted under 35 U.S.C. § 271(g), infringement hinges on the importation of a product "made by" a patented process. A key legal and factual question will be: assuming the TSMC process is found to infringe, are the final Xilinx FPGAs and SoCs imported into the U.S. considered products that are "not materially changed by subsequent processes" after the allegedly infringing manufacturing step, thus satisfying the requirements for liability under the statute?