DCT
1:19-cv-01834
Taiwan Semiconductor Mfg Co Ltd v. GlobalFoundries US Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Taiwan Semiconductor Manufacturing Company Limited (Taiwan)
- Defendant: GlobalFoundries U.S. Inc. (Delaware)
- Plaintiff’s Counsel: Shaw Keller LLP; Quinn Emanuel Urquhart & Sullivan, LLP
- Case Identification: 1:19-cv-01834, D. Del., 09/30/2019
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is a Delaware corporation and therefore resides in the district.
- Core Dispute: Plaintiff alleges that Defendant's semiconductor devices and integrated circuits, manufactured using its 32nm, 28nm, 22nm, 16nm, 14nm, and 12nm process technologies, infringe four U.S. patents related to semiconductor device structures and fabrication methods.
- Technical Context: The lawsuit concerns foundational technologies for manufacturing advanced integrated circuits, a highly competitive field dominated by a few major foundries that produce the core components for the global electronics market.
- Key Procedural History: The complaint notes that in August 2019, approximately one month before this suit was filed, GlobalFoundries launched a "massive patent infringement campaign against TSMC and its customers" by filing 19 lawsuits. This action by TSMC appears to be a responsive countersuit in the broader legal conflict between the two semiconductor foundry rivals.
Case Timeline
| Date | Event |
|---|---|
| 2003-12-29 | U.S. Patent No. 6,963,114 Priority Date |
| 2005-11-08 | U.S. Patent No. 6,963,114 Issue Date |
| 2008-01-24 | U.S. Patent No. 7,897,514 Priority Date |
| 2008-09-17 | U.S. Patent No. 8,138,554 Priority Date |
| 2011-03-01 | U.S. Patent No. 7,897,514 Issue Date |
| 2012-03-20 | U.S. Patent No. 8,138,554 Issue Date |
| 2014-10-16 | U.S. Patent No. 9,634,013 Priority Date |
| 2017-04-25 | U.S. Patent No. 9,634,013 Issue Date |
| 2018-08-01 | GlobalFoundries halts development of 7nm technology (approx. date) |
| 2019-08-01 | GlobalFoundries files patent lawsuits against TSMC (approx. date) |
| 2019-09-30 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,963,114 - SOI MOSFET with multi-sided source/drain silicide
Issued November 8, 2005
The Invention Explained
- Problem Addressed: The patent’s background section explains that as semiconductor devices shrink, the contact area between metal interconnects (vias) and the source/drain regions of a transistor also shrinks, increasing electrical resistance and hindering device performance (’114 Patent, col. 1:19-29).
- The Patented Solution: The invention describes a transistor contact structure, particularly for Silicon-on-Insulator (SOI) devices, that increases the available contact surface area without enlarging the device footprint. It achieves this by creating a contact layer (e.g., silicide) that covers not only the top surface of the source/drain region but also wraps around to cover its sidewall, creating a "multi-sided" contact (’114 Patent, Abstract). The specification discloses forming this structure by etching a void that undercuts the semiconductor feature and then filling that void to create a contact with distinct top, side, and bottom components (’114 Patent, col. 5:26-34, Fig. 3).
- Technical Importance: This method provided a potential solution to mitigate rising contact resistance in scaled-down transistors, a critical bottleneck for performance improvements in advanced manufacturing nodes (’114 Patent, col. 1:30-34).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶31).
- Essential elements of independent claim 1 include:
- An insulator extending over a portion of a substrate.
- A semiconductor feature extending over a portion of the insulator.
- A contact portion with a first, second, and third portion, where the first portion connects the second and third portions.
- The first portion spans a sidewall of the semiconductor feature.
- A portion of the semiconductor feature interposes and contacts the second and third portions.
- The complaint reserves the right to identify additional infringing activities and products during discovery (Compl. ¶31).
U.S. Patent No. 9,634,013 - Contact for semiconductor fabrication
Issued April 25, 2017
The Invention Explained
- Problem Addressed: The patent addresses the difficulty of forming a reliable, low-resistance electrical contact that connects both a transistor's source/drain region and an adjacent gate structure, a common requirement in dense layouts like SRAM cells, especially within the tight confines of a FinFET architecture (’013 Patent, col. 1:21-31).
- The Patented Solution: The invention proposes a device with an asymmetric gate structure. The spacer on the side of the gate adjacent to the contact area is removed, while the spacer on the other side remains. This removal creates more physical space for a conductive "butt contact" plug to land, allowing it to make direct physical contact simultaneously with the doped fin region, the top of the gate, and the newly exposed gate sidewall, thereby maximizing contact area and improving electrical performance (’013 Patent, Abstract; col. 2:40-54).
- Technical Importance: This asymmetric spacer design enables the formation of more robust, larger-area "butt contacts" in highly scaled FinFETs, which is a key enabling technology for dense and high-performance logic and memory circuits (’013 Patent, col. 1:28-31).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶45).
- Essential elements of independent claim 1 include:
- A substrate with a fin structure containing a doped region.
- A first gate over the fin, positioned adjacent to the doped region.
- The first gate has a spacer on a first side but "no spacer on a second side between the gate and the doped region."
- The gate includes a gate dielectric layer and a gate electrode.
- A conductive plug that physically contacts the doped region, the gate dielectric layer, one of the gate electrode sidewalls, and the top of the first gate.
- The complaint reserves the right to identify additional infringing activities and products during discovery (Compl. ¶45).
Multi-Patent Capsule: U.S. Patent No. 7,897,514 - Semiconductor contact barrier
Issued March 1, 2011
- Technology Synopsis: This patent describes a method for improving the performance of barrier layers used in electrical contacts. The method involves forming a contact barrier layer (e.g., of cobalt tungsten phosphide) on a conductive region using electroless plating, and then treating that layer with a plasma containing materials like silane or germane. This treatment is intended to fill grain boundaries within the barrier layer, thereby reducing contact resistance and improving its ability to prevent material migration (e.g., of copper) (’514 Patent, Abstract; col. 2:37-51).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶60, ¶65).
- Accused Features: The complaint alleges that GlobalFoundries' 32, 28, 14, and 12 nm processes use this method, specifically by forming a titanium-based contact barrier layer and treating it to form materials such as titanium silicide (Compl. ¶67-72).
Multi-Patent Capsule: U.S. Patent No. 8,138,554 - Semiconductor device with local interconnects
Issued March 20, 2012
- Technology Synopsis: This patent discloses a device structure designed to improve device density and reduce interconnect resistance. The invention features two transistors with collinear gate lines. A shared source/drain region between them is connected to other source/drain regions by a "local interconnect"—a conductive line that is parallel to the gate lines and formed at the same level as the gate electrodes. This structure provides a larger, lower-resistance connection than a conventional, smaller-diameter conductive plug (’554 Patent, Abstract; col. 3:25-44).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶77, ¶81).
- Accused Features: The complaint alleges that GlobalFoundries’ 14 and 12 nm devices, such as the AMD RX480 and Ryzen 7 2700, employ this architecture, using conductive lines to connect source/drain regions of substantially collinear NMOS and PMOS gate structures (Compl. ¶83-85).
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are a broad category of semiconductor devices, integrated circuits, and products manufactured by Defendant GlobalFoundries using its 32/28nm, 22nm, 16nm, 14nm, and 12nm technology nodes and platforms (Compl. ¶27). The complaint identifies specific non-limiting examples including the AMD A8-3800 Llano (32nm), Rockchip RK3188 (28nm), Rockchip RK1808 (22nm), AMD RX480 (14nm), and AMD Ryzen 7 2700 (12nm) devices (Compl. ¶27).
Functionality and Market Context
The accused products are foundational semiconductor components, such as processors and systems-on-a-chip (SoCs), which are incorporated into a wide variety of downstream consumer and enterprise electronics (Compl. ¶6). The complaint alleges that GlobalFoundries is a major market competitor that has made "extensive use of TSMC's patented technologies" without license or permission after purportedly falling behind in technological development (Compl. ¶18, ¶21, ¶29).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
U.S. Patent No. 6,963,114 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an insulator extending over at least a portion of a substrate; | The accused products include a silicon oxide (SiO) layer extending over a silicon substrate. | ¶38 | col. 4:26-40 |
| a semiconductor feature extending over at least a portion of the insulator; | The accused products include a semiconductor layer extending over the silicon oxide layer. | ¶39 | col. 4:56-65 |
| a contact portion having a first portion, a second portion and a third portion, said first portion connecting said second portion and said third portion, wherein the first portion spans a sidewall of the semiconductor feature, and wherein a portion of the semiconductor feature interposes and contacts the second and third portions. | The accused products contain "gate contact structures" with a first, second, and third portion. The first portion connects the other two and spans a sidewall of the semiconductor layer, while a portion of the semiconductor layer is located between and contacts the second and third portions of the contact structure. | ¶40 | col. 5:26-34 |
Identified Points of Contention
- Technical Questions: A central factual dispute may concern the physical structure of the accused "gate contact structures." The complaint's allegations will require evidentiary support, likely from destructive reverse engineering, to demonstrate that the contacts in GlobalFoundries' devices possess the specific three-part geometry claimed in the patent, as distinguished from a more conventional two-part (top and side) silicide contact.
- Scope Questions: The infringement analysis raises the question of whether the accused structures meet all limitations of the claimed three-part contact portion. The definition of this element will be critical, specifically whether the accused products contain a feature that corresponds to the "third portion" as described and depicted in the patent specification (e.g., element 349 in Fig. 3), which is formed in a void created by an undercut etch.
U.S. Patent No. 9,634,013 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor device comprising: a substrate; a fin structure on the substrate, the fin structure comprising a doped region; | The accused products are FinFET devices containing fins on a silicon substrate, with the fins having doped source/drain regions. | ¶52, ¶53 | col. 3:20-45 |
| a first gate over the fin structure...the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region... | The accused products allegedly have gates with an asymmetric spacer configuration, where a spacer is present on one side but absent on the other side adjacent to the doped region being contacted. | ¶54 | col. 5:10-20 |
| and a conductive plug that physically contacts the doped region, the gate dielectric layer, one of the sidewalls of the gate electrode and the top of the first gate. | The accused products contain conductive plugs that physically contact the doped source/drain region, the gate dielectric, a sidewall of the gate electrode, and the top of the gate. | ¶55 | col. 5:25-34 |
Identified Points of Contention
- Technical Questions: The infringement analysis will likely turn on physical evidence of the gate structure in the accused devices. A key question is whether there is a complete absence of a spacer on one side of the gate, as required by the claim, or if some residual or modified spacer material remains.
- Scope Questions: A point of contention may be the interpretation of the negative limitation "having no spacer." The court will need to determine whether this requires the absolute physical absence of any spacer-like material or a functional absence, and whether the structure of the accused devices meets that standard. Further, it raises the question of whether the accused plug makes simultaneous "physical contact" with the four distinct surfaces recited in the claim.
V. Key Claim Terms for Construction
U.S. Patent No. 6,963,114
- The Term: "a contact portion having a first portion, a second portion and a third portion"
- Context and Importance: This term defines the fundamental geometry of the asserted invention. The existence of three distinct, connected portions is the basis for the infringement allegation. Practitioners may focus on this term because the defendant will likely argue its contacts are conventional two-part structures, making the existence and definition of the "third portion" a dispositive issue for infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The plain language of claim 1 does not explicitly state how the three portions must be geometrically arranged relative to each other, beyond the connection and interposing requirements. This may support an argument that any contact with three identifiable and connected sub-regions meets the claim.
- Evidence for a Narrower Interpretation: The specification's primary embodiment, shown in Figure 3, depicts a very specific arrangement where the "third portion" (349) is a distinct feature formed in an undercut void beneath the "semiconductor feature" (330). A court may read this limitation from the specification into the claim, narrowing its scope to structures formed in a similar manner (’114 Patent, col. 5:26-65).
U.S. Patent No. 9,634,013
- The Term: "having no spacer on a second side"
- Context and Importance: This negative limitation is the core of the asserted asymmetric gate structure and is critical for infringement. Proving the absence of a feature can be challenging. Practitioners may focus on this term because its interpretation—whether it requires a literal, complete absence of material or a functional absence—will be central to both infringement and validity arguments.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue that "no spacer" should be interpreted functionally, meaning the absence of a structure that provides the electrical isolation or etch-stop functions of a conventional spacer, even if some residual dielectric material remains after the removal process.
- Evidence for a Narrower Interpretation: The specification describes a process of explicitly removing a spacer (element 114) from one side (’013 Patent, col. 5:10-20, Fig. 1D). This supports a literal interpretation requiring the complete physical absence of the spacer structure that was originally formed on that side of the gate.
VI. Other Allegations
Indirect Infringement
The complaint makes boilerplate allegations of induced infringement for all asserted patents, stating that GlobalFoundries knowingly and intentionally encourages its customers and others to make, use, sell, or import the accused products (e.g., Compl. ¶32, ¶46, ¶61, ¶78).
Willful Infringement
For each patent, the complaint alleges that GlobalFoundries has had knowledge of the patent and its infringement "at least by filing this Complaint" (e.g., Compl. ¶34, ¶48, ¶63, ¶80). This pleading strategy aims to establish a basis for post-filing willfulness and a potential claim for enhanced damages under 35 U.S.C. § 284. The complaint also seeks a finding that the case is "exceptional" to recover attorneys' fees under 35 U.S.C. § 285 (e.g., Compl. ¶43).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of structural proof: Can TSMC present clear and convincing evidence from reverse engineering that GlobalFoundries’ commercial devices—manufactured across multiple complex process nodes—actually embody the specific and nuanced structural features required by the patent claims, such as the three-part contact of the ’114 patent and the precise "no spacer" asymmetric gate of the ’013 patent?
- A central legal question will be one of claim scope: How will the court construe the negative limitation "having no spacer" in the ’013 patent? The case may turn on whether this term requires the literal and complete physical absence of any spacer material, a standard that can be difficult to meet, or a less stringent functional absence.
- The dispute raises a significant strategic question for the industry: As this lawsuit is a direct counter-move to a broad patent assertion campaign by GlobalFoundries against TSMC, the outcome and progression of this case will be closely watched for its potential to either escalate the conflict or compel a global cross-license and settlement between two of the world's leading semiconductor foundries.