DCT
1:19-cv-01835
Taiwan Semiconductor Mfg Co Ltd v. GlobalFoundries US Inc
I. Executive Summary and Procedural Information
Parties & Counsel:
- Plaintiff: Taiwan Semiconductor Manufacturing Company Limited (Taiwan)
- Defendant: GlobalFoundries U.S. Inc. (Delaware)
- Plaintiff’s Counsel: Quinn Emanuel Urquhart & Sullivan, LLP; Shaw Keller LLP
Case Identification: 1:19-cv-01835, D. Del., 09/30/2019
Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is a Delaware corporation and therefore resides in the district.
Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices, manufactured using its advanced process nodes, infringe four patents related to foundational transistor structures and manufacturing methods, including FinFET technology.
Technical Context: The lawsuit concerns the fabrication of leading-edge semiconductor devices, such as FinFETs (Fin Field Effect Transistors), which are three-dimensional transistor structures essential for modern high-performance computer processors and electronics.
Key Procedural History: The complaint alleges that in August 2019, Defendant launched a "massive patent infringement campaign" against Plaintiff. This lawsuit by Plaintiff followed approximately one month later. The complaint also contains narrative allegations regarding Defendant's business decisions, including halting its 7-nanometer technology development and selling off manufacturing assets.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-13 | U.S. Patent No. 6,720,619 Priority Date |
| 2003-02-27 | U.S. Patent No. 7,105,894 Priority Date |
| 2003-08-01 | U.S. Patent No. 7,170,118 Priority Date |
| 2004-04-13 | U.S. Patent No. 6,720,619 Issue Date |
| 2006-09-12 | U.S. Patent No. 7,105,894 Issue Date |
| 2007-01-30 | U.S. Patent No. 7,170,118 Issue Date |
| 2013-02-22 | U.S. Patent No. 9,166,053 Priority Date |
| 2015-10-20 | U.S. Patent No. 9,166,053 Issue Date |
| 2018-08-01 | Defendant allegedly halts 7nm technology development |
| 2019-08-01 | Defendant allegedly launches patent campaign against Plaintiff |
| 2019-09-30 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,170,118 - "Field effect transistor (FET) device having corrugated structure and method for fabrication thereof"
The Invention Explained
- Problem Addressed: The patent addresses the ongoing challenge of fabricating semiconductor devices with enhanced performance as device dimensions shrink, a fundamental issue in the progression of Moore's Law (ʼ118 Patent, col. 1:10-34).
- The Patented Solution: The invention proposes creating a "corrugated" or wave-like surface on the transistor's channel region and/or the top surface of the gate electrode (ʼ118 Patent, Abstract; col. 3:20-28). This three-dimensional texturing is designed to increase the effective channel length and/or gate electrode length without increasing the device's footprint, which is anticipated to improve device performance, such as saturated drain current (ʼ118 Patent, col. 12:1-12). The concept is illustrated in the patent's figures, which show a repeating, undulating profile (ʼ118 Patent, Fig. 1, 8).
- Technical Importance: This approach represents a method to enhance transistor performance through geometric modifications in three dimensions, a precursor to more complex 3D transistor architectures like FinFETs.
Key Claims at a Glance
- The complaint asserts independent method claim 11 (Compl. ¶31).
- Essential Elements of Claim 11:
- Providing a semiconductor substrate with an active region defined by isolation regions.
- Forming a gate electrode over the active and isolation regions to define a channel region.
- Forming a pair of source/drain regions separated by the channel region.
- Wherein an interface of the active region is "corrugated," comprising "rounded valley bottom portions and peak portions."
- The complaint does not explicitly reserve the right to assert dependent claims but makes allegations regarding "one or more claims" of the patent (Compl. ¶32).
U.S. Patent No. 7,105,894 - "Contacts to semiconductor fin device"
The Invention Explained
- Problem Addressed: The patent identifies contact resistance as a major fraction of the total series resistance in nanoscale devices, which degrades drive current and performance (ʼ894 Patent, col. 1:51-59). Conventional contacts are made to a single top surface, limiting the contact area.
- The Patented Solution: The invention describes forming contacts that connect to multiple surfaces of a semiconductor fin—specifically, the top surface and one or both sidewall surfaces (ʼ894 Patent, col. 6:1-17). By increasing the surface area of the electrical connection to the fin, the contact resistance is reduced. The method involves using an etch stop layer to protect the fin and underlying insulator during the contact hole etching process, enabling the creation of these multi-sided contacts (ʼ894 Patent, Abstract; col. 7:20-48).
- Technical Importance: The invention directly tackles the critical issue of parasitic resistance in FinFETs, a problem that becomes increasingly important as transistors are scaled to smaller dimensions where such resistances can dominate device performance.
Key Claims at a Glance
- The complaint asserts independent apparatus claim 1 (Compl. ¶46).
- Essential Elements of Claim 1:
- A semiconductor fin with a top surface and two sidewall surfaces on an insulating substrate, the fin comprising a channel, source, and drain region.
- A dielectric layer on the fin and a portion of the insulating substrate.
- A contact made of conductive material, in electrical communication with the fin through an opening in the dielectric layer, where the contact is on at least one surface of the fin that includes "at least one of the two sidewall surfaces."
- The complaint makes allegations regarding "one or more claims" of the patent (Compl. ¶47).
U.S. Patent No. 9,166,053 - "FinFET device including a stepped profile structure"
- Technology Synopsis: This patent addresses the problem of non-uniform voltage thresholds in FinFETs, which can arise from device geometry (ʼ053 Patent, col. 1:21-28). The invention is a FinFET device where the gate structure has a "stepped profile," meaning its width varies at different points. This specific shaping of the gate is designed to create a more uniform electric field, improve gate control, and achieve more consistent voltage thresholds across devices (ʼ053 Patent, Abstract; col. 8:46-56).
- Asserted Claims: At least independent claim 1 (Compl. ¶59, ¶63).
- Accused Features: The complaint alleges that Defendant's 14nm and 12nm FinFET transistors incorporate a gate structure with a stepped profile, where the width at the bottom of the gate structure is wider than the width at the top (Compl. ¶68).
U.S. Patent No. 6,720,619 - "Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices"
- Technology Synopsis: This patent addresses "floating body effects" in silicon-on-insulator (SOI) devices, which can degrade electrical performance (ʼ619 Patent, col. 1:40-54). The invention describes a multiple-gate device structure (akin to a FinFET) where the gate electrode wraps around a fin-like active region. A key feature is that the exposed top portion of this active region has its "top corners rounded" to avoid sharp-corner effects that can negatively impact device operation (ʼ619 Patent, Abstract; col. 5:6-12).
- Asserted Claims: At least independent claim 1 (Compl. ¶75, ¶79).
- Accused Features: The complaint alleges that Defendant's FinFETs, fabricated on its 14nm and 12nm processes, are multiple-gate device structures where the exposed active region has rounded top corners (Compl. ¶80, ¶85).
III. The Accused Instrumentality
Product Identification
The accused products are semiconductor devices, integrated circuits, and systems-on-a-chip (SoCs) manufactured by Defendant using its 32nm, 28nm, 22nm, 16nm, 14nm, and 12nm technology nodes and platforms (Compl. ¶27). The complaint provides non-limiting examples including the AMD A8-3800 Llano (32nm), Rockchip RK3188 (28nm), AMD RX480 (14nm), and AMD Ryzen 7 2700 (12nm) (Compl. ¶27).
Functionality and Market Context
The accused instrumentalities are the fundamental building blocks of modern electronics, serving as processors, graphics cards, and controllers in a wide array of consumer and enterprise products (Compl. ¶6, ¶37). The relevant functionality is not consumer-facing but lies in the sub-micron physical structures of the transistors themselves, such as the shape of the gate electrodes, the geometry of the fins, and the formation of electrical contacts (Compl. ¶37, ¶51, ¶64, ¶80). The complaint alleges these technologies are critical for high-performance computing and that Defendant uses them to compete in the market after abandoning its own development of more advanced nodes (Compl. ¶18, ¶21).
No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
'118 Patent Infringement Allegations
| Claim Element (from Independent Claim 11) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method for forming a field effect transistor (FET) device comprising: providing a semiconductor substrate comprising an active region defined by isolation regions; | The accused products are formed by providing a silicon semiconductor substrate. The active regions are formed by fins built up from the substrate and defined by isolation regions (e.g., silicon oxide) between the fins. | ¶38 | col. 5:11-15 |
| forming a gate electrode over a portion of the active region and at least a portion of the isolation regions to cover and define a channel region within the active region; | The accused products' fin structures are at least partially surrounded by a gate electrode, which is positioned over the active region (the fin) and the isolation regions between fins. This defines a channel region within the fin structure. | ¶39 | col. 5:51-63 |
| and forming a pair of source/drain regions within the active region and separated by the channel region within the active region | The accused products' fin structures connect source and drain regions, which are separated by the channel region within the active region. | ¶40 | col. 5:60-63 |
| wherein an interface of the active region is corrugated, said corrugated interface comprising rounded valley bottom portions and peak portions. | The complaint alleges that the interface between the gate electrode and the fin structures is "corrugated" and contains "rounded valley bottom portions and peak portions." | ¶41 | col. 11:36-42 |
Identified Points of Contention
- Scope Questions: The central dispute may concern the meaning of "corrugated." A question for the court will be whether the inherent, three-dimensional topography of a gate electrode wrapping over a rectangular fin—a standard FinFET geometry—satisfies the claim term "corrugated," which the patent figures depict as a deliberately engineered, periodic, wave-like structure.
- Technical Questions: What evidence will show that the interface in Defendant's products possesses "rounded valley bottom portions and peak portions" as required by the claim, and does this structure arise from a process analogous to the one described in the patent?
'894 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a contact to a semiconductor fin ... comprising: the semiconductor fin comprising a top surface and two sidewall surfaces formed on an insulating substrate, said fin comprising a channel region, a source region and a drain region; | The accused products are FinFETs containing silicon fins that extend from an insulating substrate and connect source and drain regions through a channel. | ¶52 | col. 1:59-61 |
| a dielectric layer on said fin and on a portion of said insulating substrate; | A dielectric layer of silicon oxide is allegedly used on the fin and the insulating substrate in Defendant's 14nm and 12nm FinFET processes. | ¶53 | col. 8:14-25 |
| and the contact formed of an electrically conductive material ... said contact on at least one surface of said fin ... said at least one surface comprising at least one of the two sidewall surfaces. | The accused products allegedly include source/drain subcontacts (SCs) that surround each fin and "directly contacting both fin sidewalls, for example, at least at the sidewalls of the epitaxy tips of the fins." These contacts are electrically connected to the fin sidewalls with materials like TiN or TiSi. | ¶54 | col. 6:1-8 |
Identified Points of Contention
- Scope Questions: Does a contact made to the "sidewalls of the epitaxy tips of the fins" (Compl. ¶54) meet the claim limitation of a contact on the "sidewall surfaces" of the "semiconductor fin"? The analysis may turn on whether the epitaxially grown source/drain material is considered an integral part of the "semiconductor fin" for claim construction purposes.
- Technical Questions: What is the precise physical relationship between the "semiconductor fin" and the "epitaxy tips" in the accused devices? Evidence from device teardowns will be critical to determine the exact location and nature of the electrical contact.
V. Key Claim Terms for Construction
For the '118 Patent
- The Term: "corrugated interface"
- Context and Importance: This term is the central point of novelty. Infringement depends entirely on whether the physical interface between the gate and the fin in a standard FinFET can be characterized as "corrugated" as the patent defines it.
- Intrinsic Evidence for a Broader Interpretation: The patent abstract and summary are general, stating that at least one surface "is corrugated" (ʼ118 Patent, Abstract). A party could argue this covers any non-planar interface that increases effective channel length.
- Intrinsic Evidence for a Narrower Interpretation: The patent repeatedly illustrates "corrugation" as a series of deliberate, rounded, periodic grooves and ridges, created by specific processing steps like thermal annealing of masked regions (ʼ118 Patent, Fig. 3, 6, 8; col. 7:1-20). A party could argue the term requires this specific, engineered structure, not the natural topography of a gate draped over a fin.
For the '894 Patent
- The Term: "a contact ... on at least one surface of said fin ... said at least one surface comprising at least one of the two sidewall surfaces"
- Context and Importance: This term is critical because it requires a multi-sided contact that includes the fin sidewall, which is the invention's solution to reducing contact resistance. The complaint's allegation of contact with "epitaxy tips" (Compl. ¶54) puts the definition of the "fin" and its "sidewall surfaces" at the center of the dispute.
- Intrinsic Evidence for a Broader Interpretation: The patent's objective is to reduce series resistance by increasing contact area (ʼ894 Patent, col. 5:66-6:8). A party might argue that any contact structure that makes contact with vertical surfaces of the source/drain region, whether on the original fin or on epitaxially grown material, achieves this purpose and falls within the claim's scope.
- Intrinsic Evidence for a Narrower Interpretation: The patent figures, such as Figure 6A, explicitly show the contact (72) on the sidewalls (68, 70) of the primary fin structure (64) itself. A party could argue that the "semiconductor fin" is limited to this etched structure, and that contacts made only to separately grown epitaxial material do not meet the limitation.
VI. Other Allegations
Indirect Infringement
The complaint alleges that Defendant induces infringement by "actively encouraging others" to use the accused products and contributes to infringement by selling components that are a "material part of the inventions" and not a staple article of commerce (Compl. ¶32-33, ¶47-48, ¶60-61, ¶76-77). The complaint does not plead specific facts, such as references to user manuals or datasheets, to support these allegations.
Willful Infringement
The complaint alleges that Defendant has had knowledge of the asserted patents and its infringement at least since the filing of the complaint on September 30, 2019 (Compl. ¶34, ¶49, ¶62, ¶78). This forms the basis for a claim of post-filing willfulness. No facts suggesting pre-suit knowledge are alleged.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: Can the term "corrugated interface" from the ’118 patent, which is depicted as an engineered, periodic structure, be construed to read on the inherent three-dimensional topography of a standard FinFET gate? This question of claim construction will likely be dispositive for that patent.
- A key evidentiary question will be one of structural identity: For the ’894 patent, does a contact made to the sidewalls of epitaxially grown source/drain regions constitute a contact on the "sidewall surfaces" of the "semiconductor fin" itself? Resolving this will require detailed expert analysis of the accused devices' physical structures.
- A third central question will be one of technological nuance: For all asserted patents, the dispute centers on specific, subtle geometric features of transistors at the nanometer scale (e.g., rounded corners, stepped profiles). The case will likely devolve into a highly technical, expert-driven battle over whether the specific implementations in Defendant's products meet the precise language of the claims.