DCT

1:19-cv-01836

Taiwan Semiconductor Mfg Co Ltd v. GlobalFoundries US Inc

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-01836, D. Del., 09/30/2019
  • Venue Allegations: Venue is asserted on the basis that Defendant is a Delaware corporation and therefore resides in the District of Delaware.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices, manufactured using its 32nm to 12nm process nodes, infringe four patents related to SRAM cell architecture, shallow trench isolation, dual damascene interconnect manufacturing, and chip edge seals.
  • Technical Context: The technologies at issue are fundamental to modern semiconductor fabrication, governing how memory cells are laid out, how transistors are electrically isolated, how metal layers are connected, and how chips are protected from physical damage and contamination.
  • Key Procedural History: The complaint alleges that this action follows a "massive patent infringement campaign" launched by GlobalFoundries against TSMC and its customers in August 2019, suggesting this case may be a retaliatory countersuit.

Case Timeline

Date Event
2003-12-05 Priority Date for U.S. Patent No. 7,233,032
2004-01-14 Priority Date for U.S. Patent No. 7,235,864
2004-08-17 Priority Date for U.S. Patent No. 7,056,821
2006-06-06 Issue Date for U.S. Patent No. 7,056,821
2007-06-19 Issue Date for U.S. Patent No. 7,233,032
2007-06-26 Issue Date for U.S. Patent No. 7,235,864
2008-02-18 Priority Date for U.S. Patent No. 8,187,948
2012-05-29 Issue Date for U.S. Patent No. 8,187,948
2018-08-01 GlobalFoundries allegedly halts 7nm technology development
2019-08-01 GlobalFoundries allegedly launches patent litigation campaign against TSMC
2019-09-30 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,233,032 - “SRAM device having high aspect ratio cell boundary”

Issued June 19, 2007

The Invention Explained

  • Problem Addressed: The patent’s background section describes the continuous industry effort to reduce the cost of static random access memory (SRAM) devices by increasing the packing density of memory cells on a chip, which requires innovations in cell layout beyond simple scaling of feature sizes (’032 Patent, col. 1:15-46).
  • The Patented Solution: The invention discloses a specific, compact layout for an SRAM cell characterized by a high aspect ratio boundary (the ratio of the cell’s length to its width), which is greater than 3.2 (’032 Patent, Abstract). This is achieved through a particular arrangement of n-doped and p-doped regions on the substrate and the placement of various transistors (pass-gate, pull-down, pull-up, and read port) within those regions, as illustrated in the patent’s figures (’032 Patent, col. 2:35-53; Fig. 1).
  • Technical Importance: By defining a cell layout with a high aspect ratio, the invention enabled more SRAM cells to be packed onto a single wafer, reducing per-chip manufacturing costs for a given memory capacity (’032 Patent, col. 1:40-46).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶31).
  • The essential elements of claim 1 are:
    • A substrate having an n-doped region interposing first and second p-doped regions.
    • An SRAM unit cell comprising specifically located transistors: a first pass-gate and pull-down transistor over the first p-doped region; first and second pull-up transistors over the n-doped region; and a second pass-gate, second pull-down, and first and second read port transistors over the second p-doped region.
    • A first transistor active region in the first p-doped region connecting the first pass-gate and first pull-down transistors.
    • A second transistor active region in the second p-doped region connecting the second pass-gate and second pull-down transistors.
  • The complaint reserves the right to identify additional infringing claims (Compl. ¶31).

U.S. Patent No. 8,187,948 - “Hybrid gap-fill approach for STI formation”

Issued May 29, 2012

The Invention Explained

  • Problem Addressed: The patent’s background highlights the challenge in advanced semiconductor manufacturing (40 nm and below) of filling deep, narrow trenches for shallow trench isolation (STI) without creating voids or mechanically weak seams in the dielectric material (’948 Patent, col. 1:25-50).
  • The Patented Solution: The patent describes a multi-step method to create a robust STI fill. After forming a trench, a dielectric material is conformally deposited. A key step is a "first treatment," defined as an "implantation to the dielectric material," which provides enough energy to break chemical bonds. This is followed by a "steam anneal" to reform and strengthen the bonds, eliminating weak seams. (’948 Patent, Abstract; col. 4:40-4:54).
  • Technical Importance: This approach provided a method to form reliable, void-free isolation structures in high-aspect-ratio features, a critical enabler for the continued scaling of integrated circuits to smaller and denser process nodes (’948 Patent, col. 2:5-10).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶44).
  • The essential steps of method claim 1 are:
    • Providing a semiconductor substrate with a top surface.
    • Forming an opening extending from the top surface into the substrate.
    • Performing a conformal deposition to fill a dielectric material into the opening.
    • Performing a first treatment on the dielectric material, where the treatment comprises an implantation.
    • Performing a steam anneal on the dielectric material after the first treatment.
  • The complaint reserves the right to assert additional claims (Compl. ¶44).

U.S. Patent No. 7,056,821 - “Method for manufacturing dual damascene structure with a trench formed first”

Issued June 6, 2006

  • Technology Synopsis: This patent addresses challenges in creating multi-level metal interconnects, such as copper oxidation and process complexity (’821 Patent, col. 1:59-2:6). The invention discloses a "trench-first" dual damascene manufacturing method that uses a temporary sacrificial layer to define the via structure, which is intended to reduce the exposure time of copper layers to air and simplify the overall process flow (’821 Patent, col. 2:18-28).
  • Asserted Claims: At least independent method claim 1 is asserted (Compl. ¶60).
  • Accused Features: The manufacturing processes used by GlobalFoundries for its 28, 14, and 12 nm technology nodes are accused of practicing the claimed method (Compl. ¶60).

U.S. Patent No. 7,235,864 - “Integrated circuit devices, edge seals therefor”

Issued June 26, 2007

  • Technology Synopsis: The patent addresses the problem of mechanical or electrical failure of edge seals on semiconductor chips, which are meant to protect the internal circuitry from contamination and stress during sawing and packaging (’864 Patent, col. 1:6-14). The invention is a robust edge seal structure comprising multiple layers of metal lines connected vertically by not only an array of metal plugs but also by at least one continuous "metal wall," creating a more resilient barrier at the chip's periphery (’864 Patent, Abstract; col. 2:40-51).
  • Asserted Claims: At least independent product claim 1 is asserted (Compl. ¶76).
  • Accused Features: The "die seal" structures surrounding the integrated circuits in Defendant's chips, fabricated using 32, 28, 14, or 12 nm processes, are alleged to embody the claimed invention (Compl. ¶¶76, 82).

III. The Accused Instrumentality

  • Product Identification: The complaint broadly accuses all GlobalFoundries semiconductor devices and integrated circuits manufactured using its 32 nanometer technology nodes and smaller (Compl. ¶27). This includes devices made with 32/28nm High-k Metal Gate (HGMK), 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI), and 16nm, 14nm, and 12nm FinFET processes (Compl. ¶27).
  • Functionality and Market Context: The accused instrumentalities are the foundational components of modern electronics, including central processing units (CPUs), graphics processing units (GPUs), and systems-on-a-chip (SoCs) (Compl. ¶27). Specific non-exhaustive examples cited include the AMD A8-3800 Llano (32nm), Rockchip RK3188 (28nm), AMD RX480 (14nm), and AMD Ryzen 7 2700 (12nm) devices (Compl. ¶27). The complaint alleges that Defendant relies on these technologies after abandoning its own development of more advanced 7-nanometer processes (Compl. ¶18).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’032 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a substrate having an n-doped region interposing first and second p-doped regions The accused SRAM devices include PMOS pull-up transistors in n-doped regions and NMOS pull-down and pass-gate transistors in p-doped regions, establishing the claimed substrate structure. ¶37 col. 2:38-40
a first pass-gate transistor and a first pull-down transistor located at least partially over the first p-doped region The NMOS pass-gate and pull-down transistors are fabricated in p-doped regions of the substrate. ¶38 col. 2:40-42
first and second pull-up transistors located at least partially over the n-doped region The PMOS pull-up transistors are fabricated in n-doped regions of the substrate. ¶38 col. 2:42-43
a second pass-gate transistor, a second pull-down transistor, and first and second read port transistors, all located at least partially over the second p-doped region These transistors are alleged to be NMOS-type and are thus fabricated in p-doped regions. ¶38 col. 2:43-48
a first transistor active region...extending between source/drain contacts of the first pass-gate transistor and the first pull-down transistor For FinFET products, it is alleged that the fins of the first pass-gate transistor connect to the fins of the first pull-down transistor, meeting this limitation. ¶39 col. 4:45-50

Identified Points of Contention

  • Scope Questions: Claim 1 recites "first and second read port transistors," which suggests a specific eight-transistor (8T) SRAM cell architecture. The complaint, however, accuses devices containing "six-transistor (6T) or eight-transistor (8T) SRAM" arrays (Compl. ¶36). A key legal question will be whether the claim term "read port transistors" can be construed to read on components within a standard 6T SRAM cell, which typically lacks a dedicated read port circuit, or if the patent's scope is limited to particular 8T designs.
  • Technical Questions: The complaint alleges that for FinFET devices, the connection of transistor "fins" satisfies the claim limitation of an "active region implanted... and extending between source/drain contacts" (Compl. ¶39). The court may need to determine if a shared, continuous fin structure is the technical equivalent of the claimed "implanted" active region that connects discrete transistors.

’948 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a method of forming an integrated circuit structure... comprising: providing a semiconductor substrate... The accused products are semiconductor devices fabricated on a silicon substrate. ¶51 col. 3:15-17
forming an opening extending from the top surface into the semiconductor substrate The accused products contain Shallow Trench Isolation (STI) formations, which constitute openings in the substrate. ¶52 col. 3:20-22
performing a conformal deposition method to fill a dielectric material into the opening A dielectric material such as silicon dioxide (SiO2) is allegedly used to fill the STI opening via a conformal deposition method. ¶53 col. 4:19-21
performing a first treatment on the dielectric material, wherein the first treatment comprises an implantation to the dielectric material The complaint alleges the dielectric material is "implanted with, for example, Trisilylamine (TSA), NHx, and ozone (O3)." ¶54 col. 4:40-45
after the first treatment, performing a steam anneal on the dielectric material A steam anneal is allegedly performed on the dielectric material after the implantation step. ¶55 col. 5:29-31

Identified Points of Contention

  • Technical Questions: The infringement allegation hinges on whether GlobalFoundries’ process includes the highly specific step of implanting with "Trisilylamine (TSA), NHx, and ozone (O3)" (Compl. ¶54). A primary question for discovery will be to determine if the accused manufacturing process actually uses this specific sequence and these specific chemical precursors.
  • Scope Questions: The term "implantation" will be a central focus. The patent’s specification provides examples such as implanting inert gas ions or using UV light to break bonds (’948 Patent, col. 4:40-67). The complaint alleges the use of specific chemical precursors. This raises the question of whether the introduction of these chemicals in a treatment step constitutes "an implantation" as that term is understood in the patent, or if it is a distinct chemical process outside the claim's scope.

V. Key Claim Terms for Construction

Patent: U.S. Patent No. 7,233,032

  • The Term: "first and second read port transistors"
  • Context and Importance: This term appears in independent claim 1. Its construction is critical because the claim appears to describe an 8T SRAM cell, while the complaint broadly accuses products containing both 6T and 8T SRAM arrays. Practitioners may focus on this term because if it is construed to require a structure distinct from the core six transistors of a standard SRAM cell, infringement allegations against 6T-based products may fail.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not appear to provide an explicit definition of the term in the specification, which could support an argument for applying its plain and ordinary meaning to one skilled in the art.
    • Evidence for a Narrower Interpretation: The embodiment detailed in Figure 6 of the patent clearly depicts two transistors (640, 645) that form a separate read port, distinct from the pass-gate (630, 635) and pull-down (620, 625) transistors (’032 Patent, Fig. 6). This may support a narrower construction limited to an 8T architecture with a dedicated read buffer.

Patent: U.S. Patent No. 8,187,948

  • The Term: "an implantation to the dielectric material"
  • Context and Importance: This limitation defines the core of the novel "first treatment" step in method claim 1. Its meaning is pivotal because the complaint's infringement theory relies on accusing a process that uses specific chemical precursors (TSA, NHx, O3). The dispute will likely center on whether this chemical treatment process falls within the scope of "an implantation."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim uses the general article "an," and does not explicitly limit the term to conventional ion beam implantation. Plaintiff may argue the term should be read functionally to cover any process that introduces a species into the material to achieve the patent's stated goal of breaking bonds.
    • Evidence for a Narrower Interpretation: The patent's specification describes the purpose of the treatment as providing "an energy high enough for breaking bonds" and gives examples of implanting inert gas or oxygen ions, or using UV light (’948 Patent, col. 4:40-67). This context suggests that "implantation" refers to a physical, energy-driven process, which a defendant could argue is distinct from the chemical reaction process alleged in the complaint.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents, based on allegations that Defendant actively encourages others (e.g., customers) to make, use, sell, or import the accused products (e.g., Compl. ¶¶32, 45, 61, 77). For the process patents (’948 and ’821), the complaint also alleges infringement under 35 U.S.C. § 271(g) for importing products made by the claimed processes (Compl. ¶¶48, 64).
  • Willful Infringement: The complaint asserts willfulness based on knowledge of the patents as of the filing date of the complaint, September 30, 2019 (e.g., Compl. ¶¶34, 47, 63, 79). No facts are alleged to support pre-suit knowledge of the patents.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of process technology mapping: For the method patents (’948 and ’821), can TSMC prove through discovery that GlobalFoundries’ complex, proprietary manufacturing flows practice the specific steps recited in the claims? This is particularly acute for the ’948 patent, where the infringement theory rests on a specific chemical treatment being equivalent to the claimed "implantation."
  • A second central question will be one of definitional scope: For the product patents (’032 and ’864), can the claim terms be construed broadly enough to read on the accused structures? For the ’032 patent, this centers on whether "read port transistors" can cover standard 6T SRAM cells. For the ’864 patent, it will depend on whether the accused "die seals" contain the specific combination of metal plugs and "metal walls" required by the claims.
  • Finally, a key evidentiary question will be the substantiation of the complaint's detailed technical allegations. The complaint, filed on "information and belief," makes very specific assertions about the accused processes and device structures. The viability of each infringement count will depend on whether facts uncovered in discovery align with these initial, specific theories of infringement.