Taiwan Semiconductor Manufacturing Company Ltd v.Globalfoundries U.S. Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Taiwan Semiconductor Manufacturing Company Limited (Taiwan)
  • Defendant: GlobalFoundries U.S. Inc. (Delaware)
  • Plaintiff’s Counsel: Quinn Emanuel Urquhart & Sullivan, LLP
• Case Identification: 1:19-cv-01837, D. Del., 09/30/2019
• Venue Allegations: Venue is asserted as proper in the District of Delaware because Defendant is a Delaware corporation and therefore resides in the district.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices, manufactured using its 32nm, 28nm, 22nm, 16nm, 14nm, and 12nm process technologies, infringe four patents related to semiconductor device structures and manufacturing methods.
• Technical Context: The dispute concerns foundational technologies in advanced semiconductor fabrication, a highly competitive and capital-intensive industry critical to the production of processors, graphics cards, and other high-performance electronics.
• Key Procedural History: The complaint alleges that this lawsuit was filed in response to a "massive patent infringement campaign" initiated by GlobalFoundries against TSMC and its customers in August 2019. The complaint also notes that in August 2018, GlobalFoundries announced it would halt development of its 7-nanometer technology.

Case Timeline

Date	Event
2000-04-11	U.S. Patent No. 6,417,032 Priority Date
2002-07-09	U.S. Patent No. 6,417,032 Issued
2004-12-22	U.S. Patent No. 7,355,235 Priority Date
2005-08-31	U.S. Patent No. 7,501,227 Priority Date
2008-04-08	U.S. Patent No. 7,355,235 Issued
2009-03-10	U.S. Patent No. 7,501,227 Issued
2009-04-22	U.S. Patent No. 8,648,446 Priority Date
2014-02-11	U.S. Patent No. 8,648,446 Issued
2018-08-01	GlobalFoundries allegedly halts 7nm process development
2019-08-01	GlobalFoundries allegedly launches patent suit vs. TSMC
2019-09-30	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,648,446 - "Method for protecting a gate structure during contact formation," issued February 11, 2014

The Invention Explained

• Problem Addressed: In semiconductor manufacturing, conventional processes for creating electrical contacts to both the gate and the source/drain regions can inadvertently damage the gate structure. This "over-etching of the gate structure" can lead to increased contact resistance and degraded device performance (’446 Patent, col. 1:25-31).
• The Patented Solution: The invention describes a semiconductor device structure that uses two distinct protective layers to prevent this damage. A first etch stop layer (described in the specification as a "hard mask layer") is placed over the gate structure, and a separate, second etch stop layer is placed over the source and drain regions. This dual-layer system allows for the creation of contact openings to the different regions without etching and damaging the critical gate components underneath (’446 Patent, Abstract; col. 2:4-14).
• Technical Importance: This approach allows for more precise and reliable contact formation, which is crucial for manufacturing smaller and more complex integrated circuits with improved performance.

Key Claims at a Glance

• The complaint asserts infringement of at least claim 1 (Compl. ¶31).
• Independent claim 1 recites the essential elements of the device structure:
  • A substrate with a gate structure, a source region, and a drain region.
  • A "first etch stop layer" disposed over the gate structure.
  • A "second etch stop layer" disposed over the source and drain regions.
  • A dielectric layer disposed over both the first and second etch stop layers.
  • A gate contact extending through the dielectric layer and the first etch stop layer to the gate, and source/drain contacts extending through the dielectric layer and the second etch stop layer to the source/drain regions.
• The complaint reserves the right to identify additional infringing activities and products during discovery (Compl. ¶31).

U.S. Patent No. 6,417,032 - "Method of forming cross strapped Vss layout for full CMOS SRAM cell," issued July 9, 2002

The Invention Explained

• Problem Addressed: As Static Random Access Memory (SRAM) cells shrink, the electrical resistance in the metal lines that provide the ground potential (Vss) and power (Vcc) increases. This increased resistance can cause voltage drops ("IR drop") that destabilize the memory cell and reduce its immunity to noise, harming device reliability (’032 Patent, col. 3:35-52).
• The Patented Solution: The patent discloses a method for creating a "cross strapped Vss layout" to form a low-resistance power grid. The method uses multiple metallization layers to create conductors for the ground potential running in different directions (e.g., horizontally in one layer, vertically in another). These straps are connected with vias, forming a grid that significantly reduces the overall resistance of the ground connection (’032 Patent, Abstract; col. 2:38-46).
• Technical Importance: This layout provides a more robust and stable power delivery network for dense SRAM arrays, enabling higher performance and reliability in advanced semiconductor devices.

Key Claims at a Glance

• The complaint asserts infringement of at least claim 1 (Compl. ¶48).
• Independent method claim 1 recites the key steps:
  • Forming an SRAM device with standard transistor components (pull-up, pull-down, pass gate).
  • Forming a plurality of dielectric layers with metal conductor lines.
  • Forming a conductive reference potential node connected to the pull-down transistors' source regions.
  • The metal conductor lines include a "first Vss strap/conductor line oriented in a first direction" in one dielectric layer and a "second Vss strap/conductor line oriented in a second direction" in a different dielectric layer.
  • Forming a VIA/contact between the reference node and the first and second Vss straps.
• The complaint reserves the right to assert infringement of other claims (Compl. ¶49).

Multi-Patent Capsule: U.S. Patent No. 7,355,235 - "Semiconductor device and method for high-k gate dielectrics," issued April 8, 2008

• Technology Synopsis: This patent addresses defects and reliability issues in transistors that use high-k (high dielectric constant) materials for their gate insulators, which can suffer from charge trapping and voltage instability (’235 Patent, col. 1:36-46). The invention describes a multi-layer gate stack structure that includes a nitrogen-containing, substantially metal-free layer over the substrate and a high-k dielectric layer on top of it, with a specific nitrogen concentration gradient between the layers, to improve device performance and reliability (’235 Patent, Abstract).
• Asserted Claims: Independent claim 1 (Compl. ¶63).
• Accused Features: The accused products are alleged to have a gate structure comprising a silicon oxynitride (SiON) layer on the substrate, a high-k dielectric layer with a lower nitrogen percentage over the SiON layer, and a gate electrode, which allegedly maps to the claimed structure (Compl. ¶¶69-72).

Multi-Patent Capsule: U.S. Patent No. 7,501,227 - "System and method for photolithography in semiconductor manufacturing," issued March 10, 2009

• Technology Synopsis: The patent addresses the high cost associated with using advanced, high-precision lithography (such as immersion lithography) for every step in a multi-exposure patterning process (’227 Patent, col. 1:46-54). The patented solution is a method that combines a "higher-precision lithography mechanism" to create a pattern with both main and "dummy" features, and a "lower-precision lithography mechanism" in a second exposure step to remove only the dummy features, thereby balancing cost and precision (’227 Patent, Abstract).
• Asserted Claims: Independent claim 1 (Compl. ¶77).
• Accused Features: GlobalFoundries' "fin-first, cut-last" process for forming FinFETs is accused of infringing. This process allegedly uses a higher-precision step to form an array of fins (main features) and unwanted fins (dummy features), followed by a lower-precision "cut mask" step to remove the unwanted fins (Compl. ¶¶84-86).

III. The Accused Instrumentality

Product Identification

The complaint targets a wide range of products, identified as "all GlobalFoundries semiconductor devices, integrated circuits, and products manufactured at 32 nanometer technology nodes and smaller" (Compl. ¶27).

Functionality and Market Context

The accused instrumentalities are the manufacturing processes and platforms used by GlobalFoundries to fabricate chips for its customers. These processes include 32/28nm High-k Metal Gate (HGMK), 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI), and 16nm, 14nm, and 12nm Fin Field Effect Transistor (FinFET) technologies (Compl. ¶27). The complaint identifies specific end-products made with these processes, such as the AMD A8-3800 Llano (32nm), Rockchip RK3188 (28nm), AMD RX480 (14nm), and AMD Ryzen 7 2700 (12nm) devices (Compl. ¶27). The complaint alleges that GlobalFoundries abandoned development of more advanced 7nm technology and is instead reliant on these accused, older process nodes (Compl. ¶18). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,648,446 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region disposed in the substrate...	The accused products are semiconductor devices that contain PMOS and NMOS logic transistors, each having a gate structure, a source region, and a drain region disposed in a silicon substrate.	¶36, ¶38	col. 5:1-5
a first etch stop layer disposed over the gate structure;	The accused products have "a silicon nitride etch stop layer" disposed over the gate structure.	¶39	col. 7:62-65
a second etch stop layer disposed over the source region and the drain region;	The accused products have "a second silicon nitride etch stop layer" disposed over the source region and the drain region.	¶40	col. 6:35-41
a dielectric layer disposed over substrate, wherein the dielectric layer is disposed over the first etch stop layer and the second etch stop layer;	The accused products have a silicon oxide (SiO) layer disposed over both etch stop layers and a silicon carbonitride (SiCN) layer over the SiO layer.	¶41	col. 6:50-53
a gate contact... extends through the dielectric layer and the first etch stop layer to the gate structure, and the source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.	Each transistor includes a gate contact extending through the dielectric layer and first etch stop layer to the gate, and a source and drain contact extending through the dielectric and second etch stop layers.	¶42, ¶43	col. 8:5-14

U.S. Patent No. 6,417,032 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a method of forming an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits...	The accused products are SRAM devices that include an array of six-transistor (6T) or eight-transistor (8T) SRAM cells with low resistance conductors for Vss circuits.	¶54	col. 2:25-29
forming an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors...	The accused products' SRAM cells include at least two PMOS pull-up transistors, two NMOS pull-down transistors, and two pass-gate transistors.	¶55	col. 1:29-34
forming a plurality of dielectric layers containing metal conductor lines over the transistors...	The accused products' SRAM cells include various dielectric layers (ILDs, PMDs) and metallization layers containing metal conductor lines.	¶56	col. 1:34-38
said metal conductor lines including a first Vss strap/conductor line oriented in a first direction in a first one of the dielectric layers and a second Vss strap/conductor line oriented in a second direction in a second one...	The accused products include an SRAM array with "distribution lands connected to power bus Vss lines running horizontally... and oriented in a first direction... and oriented in a second direction in another... layer."	¶57	col. 2:38-46
forming a VIA/contact between the conductive reference potential node and the first and second Vss strap/conductor lines.	The accused products contain copper filled vias and tungsten filled contacts between the conductive reference potential node and the Vss strap/conductor lines.	¶58	col. 2:44-46

Identified Points of Contention

• Scope Questions: For the ’446 patent, a central question may be whether the layers in the accused products function as claimed. The patent claims a "first etch stop layer" over the gate, but the specification repeatedly refers to this layer as a "hard mask layer" (’446 Patent, col. 2:7, col. 7:62). The analysis may turn on whether the accused layer performs the functions of a "hard mask layer" as described in the patent, or merely an "etch stop layer," which could be a broader term.
• Technical Questions: For all asserted patents, the infringement allegations are made "on information and belief" based on "publicly available information" (e.g., Compl. ¶44, ¶59). A key point of contention will be a factual one: does the physical structure and manufacturing process of GlobalFoundries' devices, once revealed in discovery, actually correspond to the specific layered arrangements (’446, ’235 patents), cross-strapped conductor layouts (’032 patent), and dual-precision lithography steps (’227 patent) required by the claims?

V. Key Claim Terms for Construction

For U.S. Patent No. 8,648,446

• The Term: "first etch stop layer" (Claim 1)
• Context and Importance: This term defines the protective layer over the gate structure, which is central to the patent's solution for preventing etch damage. Practitioners may focus on this term because the specification predominantly uses the more specific term "hard mask layer" to describe this element, creating a potential ambiguity between the claim language and the detailed description.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim itself uses the plain language "etch stop layer," which could be argued to encompass any layer that serves the function of stopping an etch process, regardless of other properties.
  • Evidence for a Narrower Interpretation: The specification, including the Abstract and the detailed description of the embodiments, consistently refers to this element as a "hard mask layer" (’446 Patent, Abstract; col. 2:7-8). This may be used to argue that the claimed "first etch stop layer" must also possess the properties of a hard mask layer, which can imply use in patterning and not just as a passive stop layer.

For U.S. Patent No. 6,417,032

• The Term: "a first Vss strap/conductor line oriented in a first direction ... and a second Vss strap/conductor line oriented in a second direction" (Claim 1)
• Context and Importance: This limitation defines the core "cross-strapped" architecture of the invention. Infringement hinges on whether the accused products' Vss lines are arranged in two distinct layers with two distinct orientations. The construction of "strap," "first direction," and "second direction" will be critical.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The Summary of the Invention describes the orientation broadly, suggesting distinct directions without strictly requiring perpendicularity, stating "a first Vss strap/conductor in a first direction... [and] a second Vss strap/conductor in a second direction" (’032 Patent, col. 2:40-44).
  • Evidence for a Narrower Interpretation: The preferred embodiments and figures strongly suggest an orthogonal, grid-like structure. Figure 5, for example, explicitly labels a "Vss Vertical Strap" and a "Vss Horizontal Strap" (’032 Patent, FIG. 5). This could support an argument that the two directions must be substantially perpendicular.

VI. Other Allegations

Indirect Infringement

The complaint alleges both induced and contributory infringement for all four asserted patents. Inducement is based on allegations that GlobalFoundries knowingly encourages its customers and others to make, use, sell, and import products containing the infringing semiconductor devices (e.g., Compl. ¶32, ¶49). Contributory infringement is based on allegations that GlobalFoundries sells components that are a material part of the patented inventions and are not staple articles of commerce suitable for substantial noninfringing use (e.g., Compl. ¶33, ¶50).

Willful Infringement

The complaint alleges that GlobalFoundries' infringement will be willful from the date of the complaint's filing. It explicitly states that "By at least September 30, 2019, TSMC disclosed... the existence of the ['446] patent," thereby providing knowledge to GlobalFoundries for any continuing infringement (Compl. ¶34). The complaint also requests that the case be found "exceptional" under 35 U.S.C. § 285 (e.g., Compl. ¶46).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of structural correspondence: will the physical structures and material layers within GlobalFoundries' 12nm to 32nm process nodes, once revealed through discovery, actually map onto the specific multi-layer gate structures (’446 and ’235 patents), cross-strapped SRAM layouts (’032 patent), and FinFET patterning methods (’227 patent) required by the asserted claims?
• A key legal question will be one of definitional scope: for the ’446 patent, can the claim term "first etch stop layer" be broadly construed to cover any layer that stops an etch, or will it be narrowed by the specification's more frequent use of the term "hard mask layer," potentially limiting the scope of the claim to structures with additional, specific functionalities?
• A critical evidentiary question for the method patents (’032 and ’227) will concern process mapping: does the accused "fin-first, cut-last" technique constitute the use of distinct "higher-precision" and "lower-precision" lithography steps as claimed in the ’227 patent, and does the accused SRAM power grid design result from the claimed method of forming orthogonally oriented Vss straps as required by the ’032 patent?