DCT
1:19-cv-01986
Arbor Global Strategies LLC v. Xilinx Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Arbor Global Strategies LLC (Delaware)
- Defendant: Xilinx, Inc. (Delaware)
- Plaintiff’s Counsel: Kramer Levin Naftalis & Frankel LLP
- Case Identification: 1:19-cv-01986, D. Del., 10/18/2019
- Venue Allegations: Venue is based on Defendant being a Delaware corporation with a registered agent in the state.
- Core Dispute: Plaintiff alleges that Defendant’s Field-Programmable Gate Array (FPGA) products featuring 3D stacked-die technology infringe four patents related to reconfigurable processor modules built from stacked integrated circuit die elements.
- Technical Context: The technology concerns advanced semiconductor packaging, specifically the use of through-silicon vias (TSVs) to interconnect multiple, distinct integrated circuit dies (e.g., processors, memory, FPGAs) in a single package, enabling higher performance and bandwidth.
- Key Procedural History: The complaint was filed in October 2019. Notably, in inter partes review (IPR) proceedings filed in 2020 and 2021, after the filing of this complaint, all asserted claims of the patents-in-suit—Claim 1 of the '226 Patent, Claim 1 of the '214 Patent, Claim 1 of the '951 Patent, and Claim 23 of the '035 Patent—were subsequently cancelled by the U.S. Patent and Trademark Office.
Case Timeline
| Date | Event |
|---|---|
| 2001-12-05 | Earliest Priority Date for all Asserted Patents |
| 2004-08-24 | U.S. Patent No. 6,781,226 Issues |
| 2006-10-24 | U.S. Patent No. 7,126,214 Issues |
| 2007-10-16 | U.S. Patent No. 7,282,951 Issues |
| 2011-01-18 | U.S. Reissue Patent No. RE42,035 Issues |
| 2019-10-18 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,781,226 - Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
Issued August 24, 2004
The Invention Explained
- Problem Addressed: The patent identifies key limitations in combining discrete microprocessors and FPGAs, including the large physical size of FPGAs, long reconfiguration times, and the data-transfer bottleneck between a microprocessor's cache and an attached FPGA over a conventional bus ('226 Patent, col. 1:40 - col. 2:8).
- The Patented Solution: The invention proposes a compact module created by physically stacking thinned, bare die elements—such as a microprocessor, memory, and an FPGA—and interconnecting them with contacts that traverse the thickness of each die ('226 Patent, Abstract; Fig. 4). This architecture allows for a high density of interconnects across the entire surface of the dies, not just the periphery, thereby enabling higher data throughput between the components ('226 Patent, col. 2:35-43).
- Technical Importance: This stacked-die approach represented a method to overcome the physical and electrical barriers limiting performance in multi-chip systems, aiming to provide higher bandwidth and lower latency communication essential for high-performance computing (Compl. ¶9).
Key Claims at a Glance
- The complaint asserts at least independent Claim 1 (Compl. ¶30).
- Essential elements of Claim 1:
- at least one field programmable gate array integrated circuit die element including a programmable array;
- at least one microprocessor integrated circuit die element stacked with and electrically coupled to the FPGA die element;
- such that processing of data shared between the microprocessor and the FPGA is accelerated.
U.S. Patent No. 7,126,214 - Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
Issued October 24, 2006
The Invention Explained
- Problem Addressed: Like its parent, the '214 Patent addresses performance bottlenecks in hybrid processor systems arising from data transfer latency and lengthy FPGA reconfiguration times ('214 Patent, col. 2:1-6).
- The Patented Solution: The patent describes a module combining an FPGA with a memory die to accelerate performance. One disclosed method involves stacking thinned die elements ('214 Patent, col. 2:45-51). An alternative "Stacked Integrated Circuit Function" method is also described, where functional layers (e.g., an FPGA) are fabricated sequentially on top of a base wafer (e.g., a microprocessor) without mechanical stacking, using standard wafer processing techniques to form the layers and interconnections ('214 Patent, col. 3:9-34).
- Technical Importance: This patent expands on the core concept by detailing how stacked memory can be used to accelerate not just data processing but also FPGA reconfiguration, and it introduces an alternative monolithic 3D fabrication approach (Compl. ¶8).
Key Claims at a Glance
- The complaint asserts at least independent Claim 1 (Compl. ¶49).
- Essential elements of Claim 1:
- a first integrated circuit functional element including a field programmable gate array;
- a second integrated circuit functional element including a memory array stacked with and electrically coupled to the FPGA;
- wherein the FPGA is programmable as a processing element;
- and wherein the memory array is functional to accelerate reconfiguration of the FPGA.
U.S. Patent No. 7,282,951 - Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
Issued October 16, 2007
- Technology Synopsis: Continuing the theme of the patent family, the '951 Patent discloses a processor module with stacked die elements. Its claims focus on a configuration where a memory element is stacked with a processor and FPGA, with the memory being "functional to accelerate external memory references to the programmable array" ('951 Patent, Claim 10; Compl. ¶19). This arrangement aims to improve performance by bringing high-speed memory closer to the processing elements.
- Asserted Claims: At least Claim 1 is asserted (Compl. ¶66).
- Accused Features: The complaint alleges that Xilinx’s products, which combine FPGAs with High Bandwidth Memory (HBM) using its SSI technology, infringe by creating modules with stacked die elements that accelerate data processing (Compl. ¶69, ¶74).
U.S. Reissue Patent No. RE42,035 - Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
Issued January 18, 2011
- Technology Synopsis: As a reissue of an earlier patent in the family, the '035 Patent covers a reconfigurable processor module where multiple die elements (e.g., FPGA, processor, memory) are stacked and interconnected with through-die contacts ('035 Patent, Abstract). The invention is presented as a way to accelerate data sharing between die elements and improve manufacturing yield (Compl. ¶22).
- Asserted Claims: At least Claim 23 is asserted (Compl. ¶84).
- Accused Features: The accused Xilinx products are alleged to be FPGA processor modules that include multiple die elements coupled via TSVs to provide high bandwidth and low latency, thereby infringing the patent (Compl. ¶87-88).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Xilinx integrated circuits that utilize its "3D Stacked Silicon Interconnects ("SSI")" technology and/or integrate "High Bandwidth Memory ("HBM")" (Compl. ¶24). Specific product families named are the Virtex FPGA, Virtex UltraScale FPGA, Virtex UltraScale+ FPGA, Kintex UltraScale FPGA, Kintex UltraScale+ FPGA, and Virtex UltraScale+ HBM ICs (Compl. ¶24).
Functionality and Market Context
- The complaint alleges that Xilinx's SSI technology enables high-bandwidth connectivity between multiple dies by placing them side-by-side on a "silicon interposer" (Compl. ¶25, ¶26). This interposer contains through-silicon vias (TSVs) that electrically connect the different dies (e.g., FPGA and HBM) to each other and to the package substrate (Compl. ¶27). A visual in the complaint depicts this side-by-side die layout on a silicon interposer, with TSVs providing vertical connections through the interposer (Compl. p. 7). This architecture is alleged to be particularly valuable for data-intensive applications like machine learning by providing the high bandwidth needed to support HBM (Compl. ¶10, ¶28).
IV. Analysis of Infringement Allegations
U.S. Patent No. 6,781,226 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| at least one field programmable gate array integrated circuit die element including a programmable array; | The Accused Products are identified as including at least one FPGA IC die element from Xilinx's Virtex and Kintex product families. | ¶24, ¶35 | col. 6:9-11 |
| and at least one microprocessor integrated circuit die element stacked with and electrically coupled to said programmable array... | The Accused Products are alleged to include multiple die elements (e.g., FPGA and HBM) that are electrically coupled. The complaint alleges these dies are "stacked" and that the FPGA itself contains microprocessor functionality. | ¶33, ¶36, ¶41 | col. 6:12-17 |
| such that processing of data shared between the microprocessor and the field programmable gate array is accelerated. | The use of SSI technology with TSVs is alleged to provide "increased bandwidth and low latency operation" and to "accelerate processing" of data shared between the FPGA and other components. | ¶34, ¶38, ¶41 | col. 6:18-22 |
- Identified Points of Contention:
- Scope Question: A primary issue may be the interpretation of "stacked with." The patent's figures and description depict a vertical, 3D die-on-die configuration ('226 Patent, Fig. 4), whereas the complaint describes the accused products as having dies placed side-by-side on a silicon interposer—a 2.5D architecture (Compl. p. 7). The infringement case raises the question of whether "stacked with" can be construed to cover this side-by-side-on-interposer arrangement.
- Technical Question: It is unclear whether the accused products contain a separate "microprocessor integrated circuit die element" as required by the claim. The complaint appears to argue that microprocessor functionality within the FPGA die (e.g., "DSPs and the FGPA") satisfies this limitation (Compl. ¶41), which raises the question of whether this meets the requirement for a distinct die element.
U.S. Patent No. 7,126,214 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| at least a first integrated circuit functional element including a field programmable gate array; and | The Accused Products are identified as ICs that include at least one FPGA, such as from the Virtex and Kintex series. | ¶52, ¶54 | col. 7:56-58 |
| at least a second integrated circuit functional element including a memory array stacked with and electrically coupled to said field programmable gate array... | The Accused Products are alleged to include High Bandwidth Memory (HBM) die elements, which are memory arrays, coupled to the FPGA die elements via SSI technology. An "X-ray View" visual shows the die-to-die interconnects (Compl. p. 10). | ¶52, ¶55, ¶56 | col. 8:1-4 |
| wherein said field programmable gate array is programmable as a processing element... | The accused FPGAs are alleged to be used as processing modules with programmable Configurable Logic Blocks (CLBs). | ¶54, ¶58 | col. 8:12-14 |
| and wherein said memory array is functional to accelerate reconfiguration of said field programmable gate array... | The complaint alleges that the technology provides "increased bandwidth and low latency operation" and "accelerate[s] the processing of data" (Compl. ¶53, ¶58), but does not specifically allege facts showing the memory accelerates reconfiguration. | ¶53, ¶58 | col. 8:15-18 |
- Identified Points of Contention:
- Technical Question: A key point of contention may be the lack of factual allegations supporting the "accelerate reconfiguration" limitation. The complaint focuses on the acceleration of data processing but does not explain how the accused HBM is used to speed up the process of reconfiguring the FPGA logic itself. This suggests a potential mismatch between the accused functionality and a specific requirement of the claim.
- Scope Question: As with the '226 Patent, the meaning of "stacked with" will be critical, given the accused 2.5D architecture.
V. Key Claim Terms for Construction
The Term: "stacked with" (asserted claims of '226 and '214 Patents)
- Context and Importance: The construction of this term is central to the dispute. The patents' embodiments show dies placed vertically on top of one another ('226 Patent, Fig. 4), while the accused products use a side-by-side arrangement on a common interposer. Practitioners may focus on this term because its construction will determine whether the accused 2.5D architecture falls within the scope of claims that appear to describe a 3D architecture.
- Evidence for a Broader Interpretation: A party may argue that the term should be interpreted functionally to mean any arrangement that creates a "single very compact structure" ('226 Patent, col. 2:31-32) to solve the stated problem of interconnect latency, which would include 2.5D interposer technology.
- Evidence for a Narrower Interpretation: A party may argue that the plain meaning, supported by the patent's figures (e.g., '226 Patent, Fig. 4), limits the term to a physical, vertical superposition of one die on another, explicitly excluding side-by-side arrangements.
The Term: "accelerate reconfiguration" ('214 Patent, Claim 1)
- Context and Importance: This functional limitation requires the memory array to perform a specific task beyond general data processing. Practitioners may focus on this term because the complaint's allegations center on accelerating data processing (Compl. ¶58) and do not appear to provide facts showing how the accused HBM is used to speed up the loading of the FPGA's configuration bitstream.
- Evidence for a Broader Interpretation: The specification describes using a wide data port to update configuration cells in parallel, enabling a one-clock-cycle reconfiguration ('214 Patent, col. 4:50-58). A party might argue that any use of the high-bandwidth HBM to load the configuration data faster than a conventional serial port would meet this limitation.
- Evidence for a Narrower Interpretation: A party may argue this requires the memory array to be specifically designed or used for the purpose of FPGA reconfiguration, a function distinct from its role as general-purpose, high-speed memory for the processor. The absence of such allegations in the complaint may support a finding of non-infringement.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement of infringement for all four patents. The allegations state that Xilinx knew of or was willfully blind to the fact that it was inducing infringement by "instructing, directing and/or imposing requirement to third parties" (e.g., Compl. ¶46, ¶63, ¶81, ¶98). These allegations lack specific factual support, such as citations to user manuals, data sheets, or marketing materials that allegedly instruct customers to operate the products in an infringing manner.
- Willful Infringement: The complaint does not allege pre-suit knowledge of the patents. For each patent, it pleads that the Defendant was on notice "at least as of the service of this Complaint" (e.g., Compl. ¶45, ¶62, ¶80, ¶97). This pleading structure supports a claim for post-filing willfulness only.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of structural scope: can the term "stacked with," rooted in the patent's depiction of a vertical 3D die-on-die structure, be construed broadly enough to cover the accused products' 2.5D architecture, where dies are arranged side-by-side on a silicon interposer?
- A key evidentiary question will be one of functional mismatch: for the '214 patent, does the accused HBM, which is alleged to accelerate data processing, perform the distinct function of "accelerat[ing] reconfiguration" of the FPGA as explicitly required by the claim language, and what evidence supports this specific function?
- The most critical issue for the litigation is one of viability: given that all asserted claims across all four patents-in-suit were cancelled in IPR proceedings that concluded after the complaint was filed, the foundational basis of the lawsuit as pleaded appears to be eliminated. The central question is how, or if, the case can proceed without any valid asserted claims.