DCT

1:19-cv-02109

DIFF Scale Operation Research LLC v. MaxLinear Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-02109, D. Del., 11/07/2019
  • Venue Allegations: Venue is asserted based on Defendants being Delaware corporations that have allegedly transacted business and committed acts of infringement in the state.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor products for timing and data recovery infringe two patents related to the design and operation of phase-locked loops (PLLs).
  • Technical Context: The dispute centers on phase-locked loops, which are critical components for generating and synchronizing stable clock signals in high-speed digital communications systems like SONET/SDH.
  • Key Procedural History: The complaint notes that the asserted patent portfolio originated with ADC Telecommunications, was acquired by CommScope, and subsequently assigned to the Plaintiff. The complaint emphasizes the portfolio's value by citing a $75 million sale of a portion of ADC's patents to HTC in 2011, which were then asserted against Apple.

Case Timeline

Date Event
2001-03-02 Priority Date for ’413 and ’827 Patents
2003-12-16 Issue Date for U.S. Patent No. 6,664,827
2006-07-18 Accused Product Technical Note Date (TAN-059)
2008-08-01 Accused Product Datasheet Date (XRT91L33)
2011-02-01 Issue Date for U.S. Patent No. 7,881,413
2013-10-01 Accused Product Datasheet Date (XRT86VX38)
2018-09-01 Accused Product Datasheet Date (XRT91L31)
2019-01-01 Accused Product Brief Date (MxL7213)
2019-09-01 Accused Product Datasheet Date (MxL7213)
2019-11-07 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,881,413 - *"Digital PLL with Conditional Holdover,"* issued February 1, 2011

The Invention Explained

  • Problem Addressed: High-speed communication networks rely on a hierarchy of timing sources with varying quality levels (strata). A critical challenge is maintaining a stable timing signal if the primary reference clock is lost or its quality degrades. A standard PLL might enter "holdover" mode upon signal loss, but it lacks a mechanism to react to a simple degradation in the quality of a still-present signal (Compl. ¶27; ’413 Patent, col. 2:3-12).
  • The Patented Solution: The invention proposes a PLL with "conditional holdover." It utilizes a processor that monitors a "status message," such as a Synchronization Status Message (SSM) in a SONET/SDH network, which explicitly communicates the quality level of the incoming reference clock. Based on this message, the PLL can selectively enter a holdover state if the source's quality drops below a target level, even if the signal itself has not failed. This allows the system to intelligently switch to its more reliable internal clock rather than track a degraded external source (’413 Patent, Abstract; col. 3:1-11). The complaint highlights the predecessor company's history in developing such telecommunications products, illustrated by a graphic of selected ADC products (Compl. p. 4).
  • Technical Importance: This approach provides for more robust and reliable network timing by enabling a network element to make intelligent, quality-based decisions on when to trust an external clock versus its own internal timing, a key function for preventing timing errors from propagating through a network (’413 Patent, col. 2:34-48).

Key Claims at a Glance

  • The complaint asserts infringement of at least claim 21, which depends from independent method claim 13 (Compl. ¶52).
  • Independent Claim 13 requires:
    • Generating a timing signal from a reference clock signal in a phase locked loop.
    • Monitoring a status message from a source of the reference clock signal indicative of its quality level.
    • Placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level.
  • The complaint reserves the right to assert other claims (Compl. ¶52).

U.S. Patent No. 6,664,827 - *"Direct Digital Synthesizer Phase Locked Loop,"* issued December 16, 2003

The Invention Explained

  • Problem Addressed: Conventional PLLs can be disrupted by a sudden "step change" in the phase of the reference clock (e.g., when switching sources), forcing the loop to re-synchronize, which can cause timing errors. Furthermore, the crystal oscillators used in PLLs are prone to long-term frequency drift due to aging and temperature changes (’827 Patent, col. 2:18-23).
  • The Patented Solution: The patent describes a digital PLL that actively monitors its error signal for a step change. Upon detection, a processor can "recenter" the phase comparator to mitigate the disruption without needing to track the large phase shift. The system also addresses long-term drift by using a low-pass filter to determine the average control signal needed to maintain the correct frequency, and a processor can then "trim" the oscillator to compensate for drift over time (’827 Patent, Abstract; col. 2:35-44).
  • Technical Importance: The invention aims to improve both the short-term stability of a PLL when faced with input disruptions and its long-term frequency accuracy, enhancing overall reliability in dynamic communications environments (’827 Patent, col. 2:35-44).

Key Claims at a Glance

  • The complaint asserts infringement of at least claim 28 (Compl. ¶78).
  • Claim 28 is a machine-readable medium claim containing instructions for a processor to perform a method comprising:
    • Sampling values of an error signal indicative of a phase relationship between a reference clock signal and a feedback signal.
    • Monitoring the sampled error signal values for a step change in the phase difference.
    • Recentering a phase comparator if a step change in the phase difference is detected.
  • The complaint reserves the right to assert other claims (Compl. ¶78).

III. The Accused Instrumentality

Product Identification

  • The accused products are the XRT91L33, XRT91L31, XRT83VSH38, XRT83VSH316, and MXL7213 semiconductor devices (Compl. ¶¶38, 61).

Functionality and Market Context

  • The complaint alleges these products are used for generating timing signals in phase-locked loops and for timing circuitry (Compl. ¶¶37, 60). The allegations state, on information and belief, that the products contain the fundamental components of a PLL, such as a phase comparator, a low-pass filter, and an oscillator (Compl. ¶¶41-43, 69-71). Footnotes referencing product datasheets describe them as, for example, a "Multirate Clock and Data Recovery Unit" and a "SONET/SDH Transceiver," placing them squarely in the technological field of the patents-in-suit (Compl. fns. 15, 16).

IV. Analysis of Infringement Allegations

The complaint’s infringement allegations are made "on information and belief" and do not include a technical claim chart exhibit. The following tables summarize the narrative allegations.

’413 Infringement Allegations

Claim Element (from Independent Claim 13) Alleged Infringing Functionality Complaint Citation Patent Citation
generating the timing signal from a reference clock signal in a phase locked loop The accused products are alleged to comprise a system for generating a timing signal from a reference clock signal in a PLL. ¶48 col. 15:50-51
monitoring a status message from a source of the reference clock signal indicative of a quality level ... The accused products are alleged to include functionality for monitoring a status message indicative of a quality level. ¶49 col. 15:52-55
placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level The accused products are alleged to contain functionality for placing the PLL in a holdover condition if the quality is below a target. ¶50 col. 15:56-59

’827 Infringement Allegations

Claim Element (from Independent Claim 28) Alleged Infringing Functionality Complaint Citation Patent Citation
sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal The accused products are alleged to contain functionality for sampling an error signal indicative of a phase relationship. ¶¶73-74 col. 20:4-7
monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal The accused products are alleged to include technology for monitoring the sampled error signal values for a step change. ¶¶75-76 col. 20:8-11
recentering a phase comparator if a step change in the phase difference ... is detected The accused products are alleged to include functionality for recentering a phase comparator if a step change is detected. ¶77 col. 20:12-15

Identified Points of Contention

  • Evidentiary Questions: The complaint's allegations track the claim language and are made "on information and belief." A central issue for the court will be whether the plaintiff can substantiate these conclusory allegations with specific evidence detailing the internal operation of the accused products.
  • Scope Questions: For the ’413 patent, a dispute may arise over whether the accused products’ mechanism for detecting signal degradation, if any, qualifies as "monitoring a status message." For the ’827 patent, the dispute may center on whether any error correction performed by the accused products meets the specific limitation of "recentering a phase comparator" as opposed to another form of compensation.

V. Key Claim Terms for Construction

Term: "status message" (’413 Patent, Claim 13)

  • Context and Importance: This term is central to the "conditional holdover" concept. The infringement analysis for the ’413 patent depends on whether any signal monitored by the accused products constitutes a "status message."
  • Intrinsic Evidence for a Broader Interpretation: The claims themselves do not define the term, which may support an argument that it should be given its plain and ordinary meaning, encompassing any signal that conveys information about the quality of a clock source.
  • Intrinsic Evidence for a Narrower Interpretation: The specification repeatedly uses Synchronous Optical Network (SONET) Synchronization Status Messages (SSMs) as the primary example, describing them as signals that indicate the "acceptability status and quality level of the signal" and its "stratum level" (’413 Patent, col. 2:35-41). A party could argue this context limits the term to a structured, multi-bit message that explicitly encodes a hierarchical quality level, not a simple binary indicator like loss-of-signal.

Term: "recenter the digital phase comparator" (’827 Patent, Claim 28)

  • Context and Importance: This term describes the allegedly novel response to a phase step-change. Infringement of the ’827 patent hinges on whether the accused products’ corrective action is properly characterized as "recentering."
  • Intrinsic Evidence for a Broader Interpretation: The term is not explicitly defined, which could support a broader construction covering any adjustment to the comparator's operating point or parameters to mitigate a detected phase error without tracking it.
  • Intrinsic Evidence for a Narrower Interpretation: The specification discloses specific ways to achieve recentering, such as by "monitoring and adjusting divide-by-N counters of the frequency dividers" or by "adjusting the zero phase error point of the analog-to-digital converter" (’827 Patent, col. 8:40-52; col. 9:1-4). A party may argue that these specific disclosed embodiments limit the scope of the term to these or structurally equivalent actions.

VI. Other Allegations

Indirect Infringement

  • The complaint alleges induced infringement for both patents. The factual basis asserted is that MaxLinear provides the accused products along with "documentation and training materials," "user manuals," and "product support" that allegedly instruct customers and end-users to operate the products in a manner that directly infringes the asserted claims (Compl. ¶¶55, 81).

Willful Infringement

  • Willfulness allegations for both patents are based on alleged knowledge of the patents "since at least service of this Complaint or shortly thereafter" (Compl. ¶¶54, 80). The complaint also asserts that the patents are "well-known within the industry" due to patent citations, but provides no facts alleging pre-suit knowledge by the Defendant (Compl. ¶¶56, 82).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A core issue will be one of evidentiary sufficiency: Can the plaintiff move beyond the complaint's "information and belief" allegations, which track claim language, to produce specific, technical evidence demonstrating that the accused semiconductor products internally perform the precise methods recited in the asserted claims?
  2. A key question of claim scope for the ’413 patent will be: Can the term "status message," which is exemplified in the patent by complex SONET/SDH quality-level signals, be construed broadly enough to read on the specific mechanism, if any, used by the accused products to assess reference clock quality?
  3. A key technical question for the ’827 patent will be: Does the accused products' method for handling phase disruptions constitute "recentering a phase comparator" as taught by the patent, or does it employ a functionally different error-correction technique, raising a fundamental question of technical mismatch?