Altair Logix LLC v. Western Digital Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Western Digital Corporation (Delaware)
  • Plaintiff’s Counsel: Stamoulis & Weinblatt LLC
• Case Identification: 1:19-cv-02178, D. Del., 11/21/2019
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because the Defendant is a Delaware corporation and therefore resides in the district.
• Core Dispute: Plaintiff alleges that Defendant’s My Cloud line of network-attached storage products infringes a patent related to dynamically reconfigurable processor architectures for media processing.
• Technical Context: The technology concerns specialized integrated circuits designed to offer the performance of fixed-function hardware with the flexibility of software by reconfiguring computational elements at run-time.
• Key Procedural History: The complaint alleges that the asserted independent claim, claim 1, was an originally filed claim that issued without amendment and was not rejected during prosecution as being anticipated by any prior art.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates

• Patent Identification: U.S. Patent No. 6,289,434, “Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates,” issued September 11, 2001.

The Invention Explained

• Problem Addressed: The patent addresses the trade-offs inherent in prior art methods for implementing functions on silicon. It identifies fixed-function circuits as high-performing but costly and inflexible; general-purpose microprocessors as flexible but too slow for real-time tasks; and other solutions like DSPs and FPGAs as having their own cost-performance limitations (’434 Patent, col. 1:42-2:39). The core problem is described as "temporal redundancy," where fixed-function systems must dedicate silicon resources to all possible functions, even those not currently in use (Compl. ¶19; ’434 Patent, col. 2:50-57).
• The Patented Solution: The invention proposes an apparatus that achieves the performance of fixed-function implementations at a lower cost by dynamically reconfiguring and re-using "groups of computational and storage elements in different configurations" at run-time (’434 Patent, col. 3:1-11). This architecture, which aggregates the reconfigurable elements into a "media processing unit," is designed to adapt its configuration to varying input data and processing requirements, thereby reducing redundancy and cost (Compl. ¶¶20-21).
• Technical Importance: The technology aimed to bridge the gap between high-performance, application-specific integrated circuits (ASICs) and flexible, software-driven processors by creating a reusable hardware fabric for demanding media processing tasks (Compl. ¶12).

Key Claims at a Glance

• The complaint asserts independent claim 1.
• The essential elements of independent claim 1 are:
  • An apparatus for processing data, comprising:
  • An addressable memory for storing data and instructions with a plurality of input/outputs.
  • A plurality of media processing units, each coupled to the memory and comprising:
    • a multiplier;
    • an arithmetic unit;
    • an arithmetic logic unit capable of operating concurrently with the multiplier and/or the arithmetic unit; and
    • a bit manipulation unit capable of operating concurrently with the arithmetic logic unit and the multiplier and/or arithmetic unit.
  • Each of the plurality of media processors is for performing at least one operation simultaneously with other media processing units.
  • Each operation comprises the steps of receiving an instruction and data from memory, processing the data to produce a result, and providing the result at the processor's input/output.

III. The Accused Instrumentality

Product Identification

• Defendant's "My Cloud products" are identified as the Accused Instrumentality (Compl. ¶26).

Functionality and Market Context

• The My Cloud products are described as network-attached storage (NAS) devices that function as media centers with DLNA/UPnP support, allowing users to stream photos, videos, and music to various devices on a home network (Compl. ¶27). The complaint alleges these products incorporate a Mindspeed Comcerto 2000 system-on-chip (SoC), which contains "dual ARM cortex A9 processors" (Compl. ¶¶27-28). Each of these processors is alleged to include a "NEON media coprocessor" that acts as the claimed "media processing unit" (Compl. ¶28). The complaint provides a block diagram of the Cortex-A9 processor, identifying a "NEON DSP/FPU" as a component (Compl. ¶28, citing diagram on p. 12).

IV. Analysis of Infringement Allegations

’434 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: A primary question may be whether the term "media processing unit," which the patent describes as an "aggregate of the dynamically reconfigurable computational and storage elements" (’434 Patent, col. 3:15-18), can be interpreted to cover a standard, general-purpose ARM Cortex-A9 processor with an integrated NEON SIMD (Single Instruction, Multiple Data) engine. The defense may argue the patent’s specific disclosure of a reconfigurable routing matrix and dynamic reconfiguration limits the claim scope to a more specialized architecture than the accused general-purpose SoC.
• Technical Questions: The complaint asserts that the various sub-units (ALU, BMU, etc.) are "capable of operating concurrently" in the combinations required by the claim (Compl. ¶¶31-32). A key technical question will be what evidence supports this specific mode of concurrent operation within the accused NEON engine, beyond the general parallel processing capabilities of a modern superscalar processor.

V. Key Claim Terms for Construction

The Term: "media processing unit"

• Context and Importance: This term is the central building block of the claimed apparatus. Its construction will determine whether the patent covers a conventional SoC architecture, as alleged, or is limited to the specific reconfigurable fabric detailed in the patent's specification. Practitioners may focus on this term because the infringement theory depends on mapping it to a mass-market, general-purpose processor.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party could argue that the claim itself provides the definition by listing the required sub-components (a multiplier, an arithmetic unit, an ALU, and a BMU). Any structure containing this combination of elements, regardless of its overall architecture, could be argued to be a "media processing unit" under this interpretation ('434 Patent, col. 55:31-56:20).
  • Evidence for a Narrower Interpretation: A party could argue that the specification defines the term more narrowly. The patent repeatedly ties the "media processing unit" to dynamic run-time reconfiguration, re-usability, and a "reconfigurable routing matrix" ('434 Patent, col. 3:1-18, Fig. 2). The term is first introduced as the "aggregate of the dynamically reconfigurable computational and storage elements" ('434 Patent, col. 3:15-18), suggesting that reconfigurability is an essential attribute, not just an optional feature of an embodiment.

The Term: "capable of operating concurrently"

• Context and Importance: This functional limitation appears twice in claim 1, defining the required relationship between the ALU, BMU, multiplier, and arithmetic unit. The infringement analysis will turn on whether the accused NEON engine can perform operations with the specific concurrency recited in the claim.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party may argue that "capable" simply requires the inherent ability to perform such operations, a feature of many modern superscalar processors like the Cortex-A9. The complaint relies on high-level block diagrams of the processor pipeline to suggest this capability (Compl. ¶13).
  • Evidence for a Narrower Interpretation: A party may argue that the specification links the claimed concurrency to the invention's unique "complex media instruction" format, which "may configure the media processing unit to execute three concurrent 32 bit arithmetic or logical operations in parallel" ('434 Patent, col. 4:37-42). This could support an interpretation that requires a specific type of instruction-level parallelism tied to the patent's reconfigurable architecture, rather than the general parallelism of a conventional CPU.

VI. Other Allegations

The complaint does not allege willful or indirect infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural scope: can the term "media processing unit," rooted in the patent’s disclosure of a dynamically reconfigurable hardware fabric, be construed to cover the architecture of a conventional system-on-chip containing a general-purpose ARM processor and its associated NEON SIMD engine?
• A key evidentiary question will be one of functional proof: does the accused ARM processor's NEON engine demonstrate the specific modes of concurrent operation between its multiplier, arithmetic unit, ALU, and bit manipulation unit as explicitly required by the limitations of claim 1, and what evidence will be required to prove this capability?