DCT

1:19-cv-02225

Analog Devices Inc v. Xilinx Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-02225, D. Del., 12/05/2019
  • Venue Allegations: Venue is alleged as proper in the District of Delaware on the basis that Defendant Xilinx, Inc. is a Delaware corporation.
  • Core Dispute: Plaintiff alleges that Defendant’s Zynq UltraScale+ RFSoC line of integrated circuits infringes eight patents related to high-performance analog-to-digital converter (ADC) technology.
  • Technical Context: High-performance ADCs are fundamental semiconductor components that convert analog signals, such as radio waves or sensor data, into digital information for processing in advanced electronics, particularly within wireless communications, aerospace, and defense industries.
  • Key Procedural History: The complaint alleges a prior business relationship between the parties, including the sharing of technical information under a non-disclosure agreement. For seven of the eight asserted patents, Plaintiff alleges that Defendant had pre-suit knowledge of the patents and infringement based on claim charts provided on July 31, 2019. Subsequent to the filing of this complaint, Defendant initiated Inter Partes Review (IPR) proceedings against all eight patents-in-suit. These proceedings resulted in the cancellation of all asserted independent claims of U.S. Patent Nos. 8,487,659 and 10,250,250, as well as the asserted independent claims of U.S. Patent Nos. 7,719,452 and 7,012,463.

Case Timeline

Date Event
2003-12-23 ’463 Patent Priority Date
2004-04-16 ’750 Patent Priority Date
2005-03-21 ’321 Patent Priority Date
2005-05-31 U.S. Patent No. 6,900,750 Issued
2005-11-14 ’075 Patent Priority Date
2006-03-14 U.S. Patent No. 7,012,463 Issued
2006-10-10 ’518 Patent Priority Date
2007-09-25 U.S. Patent No. 7,274,321 Issued
2007-09-26 ’452 Patent Priority Date
2007-10-23 U.S. Patent No. 7,286,075 Issued
2010-02-16 U.S. Patent No. 7,663,518 Issued
2010-05-18 U.S. Patent No. 7,719,452 Issued
2011-04-22 ’659 Patent Priority Date
2013-07-16 U.S. Patent No. 8,487,659 Issued
2016-09-12 ’250 Patent Priority Date
2019-04-02 U.S. Patent No. 10,250,250 Issued
2019-07-31 Plaintiff allegedly provided Defendant with claim charts for seven patents-in-suit
2019-12-05 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,719,452 - Pipelined Converter Systems With Enhanced Linearity

  • Issued: May 18, 2010

The Invention Explained

  • Problem Addressed: The patent’s background section describes how non-linearities and errors in the initial stages of a pipelined analog-to-digital converter can propagate through subsequent stages, degrading the overall accuracy of the final digital output (’452 Patent, col. 1:21-30).
  • The Patented Solution: The invention introduces a technique to improve linearity by injecting a known, random analog signal, or "dither," into the signal path along with the primary analog input (’452 Patent, col. 2:55-60). The pipelined stages process this combined signal. At the end of the pipeline, a digital representation of the originally injected dither is subtracted from the combined digital output, which serves to cancel out the dither’s effect while randomizing conversion errors, thereby enhancing linearity (’452 Patent, col. 3:1-7; Fig. 1).
  • Technical Importance: This approach allows for the construction of high-speed, high-resolution pipelined ADCs without requiring each individual stage to be perfectly linear, a significant challenge in semiconductor design.

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶30).
  • Essential elements of claim 1 include:
    • An analog-to-digital converter system with a sampler and successively arranged signal converters.
    • At least one digital-to-analog converter (DAC) that responds to a random digital code to inject analog dither signals into the sampler and signal converters.
    • An aligner/corrector to process digital codes from the converters into a combined digital code, which includes a first portion for the original analog samples and a second portion for the dither signals.
    • A decoder that converts the random digital code into the second portion for differencing with the combined digital code to produce a final system digital code.

U.S. Patent No. 7,663,518 - Dither Technique For Improving Dynamic Non-linearity In An Analog To Digital Converter, And An Analog To Digital Converter Having Improved Dynamic Non-linearity

  • Issued: February 16, 2010

The Invention Explained

  • Problem Addressed: The patent addresses dynamic non-linearity in successive approximation register (SAR) ADCs, which can arise from manufacturing imperfections in the switched capacitor arrays that form the core of the conversion engine (’518 Patent, col. 1:20-41).
  • The Patented Solution: The invention proposes applying a dither signal to the conversion engine during the successive approximation process, but critically, it also specifies that the dither is removed from the engine prior to the completion of all successive approximation bit trials (’518 Patent, Abstract). This removal is accomplished within the analog domain, for example, through the use of dither-removing capacitors, allowing the dither to improve linearity during key conversion steps without affecting the final digital output or requiring subsequent digital subtraction (’518 Patent, col. 3:1-10; Fig. 2).
  • Technical Importance: This method aims to linearize the conversion process internally within the analog domain, which may simplify the design of the digital back-end of SAR-based ADCs.

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶42).
  • Essential elements of claim 1 include:
    • An analog-to-digital converter with a conversion engine comprising a switched capacitor array that has redundancy.
    • A dither device for applying a dither to the conversion engine.
    • A controller to operate the engine for a successive approximation conversion of an analog input.
    • A key limitation wherein the dither is removed from the conversion engine prior to the completion of successive approximation bit trials as part of the conversion.

U.S. Patent No. 6,900,750 - Signal Conditioning System With Adjustable Gain And Offset Mismatches

  • Issued: May 31, 2005
  • Technology Synopsis: The patent describes a system for correcting offset errors in ADCs. The technique involves "chopping" the input signal using a random clock, which modulates the DC component of the input signal to a different frequency while leaving the ADC's internal offset at DC, allowing the two to be separated and the offset to be corrected (’750 Patent, col. 2:35-56).
  • Asserted Claims: At least claim 19 (Compl. ¶52).
  • Accused Features: The complaint alleges that the offset calibration loops in the Accused RFSoC Products, which allegedly use a pseudo-random bit sequence to control chopping, infringe the ’750 Patent (Compl. ¶¶54-56).

U.S. Patent No. 10,250,250 - Bootstrapped Switching Circuit

  • Issued: April 2, 2019
  • Technology Synopsis: The patent discloses a circuit for rapidly turning on a sampling switch, which is critical for high-speed ADCs. The circuit uses a bootstrapped voltage generator with a positive feedback loop to generate a boosted voltage for the switch gate, and a "jump start circuit" to accelerate the loop's activation (’250 Patent, Abstract; col. 6:19-31).
  • Asserted Claims: At least claim 1 (Compl. ¶61).
  • Accused Features: The complaint accuses the "bootstrapped switches" used as sampling switches in the sampling network of the RFSoC Products (Compl. ¶¶62-64).

U.S. Patent No. 7,274,321 - Analog to Digital Converter

  • Issued: September 25, 2007
  • Technology Synopsis: The patent describes a pipelined ADC architecture composed of multiple "converter cores." A first core performs a partial conversion on an input signal and generates a "residue" signal representing the remaining unconverted portion. This residue is then passed to a second converter core for further processing (’321 Patent, Abstract). The first core itself is comprised of at least three parallel "conversion engines" that operate cooperatively.
  • Asserted Claims: At least claim 1 (Compl. ¶71).
  • Accused Features: The complaint alleges that the three-stage pipelined SAR architecture of the RFSoC Products, which uses residue amplifiers between stages, maps onto the claimed multi-core, multi-engine structure (Compl. ¶¶73-75).

U.S. Patent No. 7,012,463 - Switched Capacitor Circuit with Reduced Common-Mode Variations

  • Issued: March 14, 2006
  • Technology Synopsis: This patent addresses the problem of common-mode voltage variations in differential amplifier circuits. It discloses a common-mode feedback circuit that senses the average output level and generates a feedback signal to a current sinking portion of the amplifier to stabilize the output (’463 Patent, Abstract).
  • Asserted Claims: At least claim 11 (Compl. ¶83).
  • Accused Features: The complaint targets the residue amplifiers within the RFSoC Products, which are alleged to use a folded-cascode operational transconductance amplifier (OTA) topology that includes a common-mode feedback circuit (Compl. ¶¶85-87).

U.S. Patent No. 8,487,659 - Comparator with Adaptive Timing

  • Issued: July 16, 2013
  • Technology Synopsis: The invention is a timing circuit that compensates for variations in process, voltage, and temperature (PVT). It generates a delay that varies inversely with these effects; for example, if the circuit logic speeds up due to a voltage increase, the delay circuit's delay increases, thereby stabilizing the overall timing of operations like a comparator latch (’659 Patent, Abstract).
  • Asserted Claims: At least claim 9 (Compl. ¶94).
  • Accused Features: The complaint accuses the "integration time calibration circuits" in the RFSoC Products, which allegedly use a delay generator circuit to control amplification time in residue amplifiers to account for PVT effects (Compl. ¶¶95-98).

U.S. Patent No. 7,286,075 - Analog to Digital Converter with Dither

  • Issued: October 23, 2007
  • Technology Synopsis: The patent discloses another dither-based technique for ADCs. After an input signal is sampled onto a switched capacitor array, a switched capacitor digital-to-analog converter injects a dither signal onto the array, creating a "known perturbation" to the stored charge before the conversion process begins (’075 Patent, Abstract).
  • Asserted Claims: At least claim 16 (Compl. ¶103).
  • Accused Features: The complaint alleges that the RFSoC Products' use of a 3.7-bit pseudo-random bit sequence to inject analog dither signals after sampling infringes this patent (Compl. ¶¶106, 107).

III. The Accused Instrumentality

  • Product Identification: Defendant Xilinx’s "Zynq UltraScale+ RFSoC" products, which include versions with RF Data Converters and with RF Data Converters and SD-FED Cores (Compl. ¶24).
  • Functionality and Market Context: The Accused RFSoC Products are System-on-a-Chip (SoC) devices that integrate a processing system, programmable logic (FPGA), and an "Integrated Direct-RF Subsystem" onto a single silicon die (Compl. ¶23). A key feature of this subsystem is the on-chip integration of high-performance ADCs, enabling "Direct RF sampling" technology (Compl. ¶¶23, 26). This allows the devices to directly digitize radio frequency signals without requiring external, discrete data converters. The complaint alleges this architecture is aimed at "High End" applications such as wireless access and aerospace and defense (Compl. ¶¶25, 26). The complaint includes a diagram from Xilinx materials illustrating how its integrated "RFADC" replaces a discrete, external ADC component in a typical signal chain (Compl. p. 6).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,719,452 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a sampler to provide samples of said analog input signal The accused products' analog-to-digital converter system has a "sampling network" that provides samples of the analog input signal. ¶32 col. 2:50-52
signal converters arranged and configured to successively process said samples The system includes a 3-stage pipelined successive approximation register (SAR) architecture where successive stages process the signal. ¶33 col. 2:52-54
at least one digital-to-analog converter configured to respond to a random digital code and inject analog dither signals into at least a selected one of said sampler and said signal converters... The system has digital-to-analog converters that receive a 3.7-bit pseudo-random bit sequence and inject analog dither signals at an input of an ADC. ¶34 col. 2:55-60
an aligner/corrector coupled to said signal converters to process said plurality of digital codes into a combined digital code that includes a first portion that corresponds to said samples and a second portion that corresponds to said analog dither signals The products include a combiner that generates a digital output signal. The complaint points to Fig. 5 of U.S. Patent No. 10,033,395 for an example of such a combiner. ¶35 col. 2:61-67
a decoder having a transfer function configured to convert said random digital code to said second portion for differencing with said combined digital code to thereby provide said system digital code The decoder subtracts a digital dither signal code from the output signal of the ADC to provide a digitized version of the sampled signals. ¶36 col. 3:1-7
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the "combiner" circuit cited in the complaint (from a separate patent) performs the specific two-part processing function required by the "aligner/corrector" limitation. The complaint alleges this element is present but provides evidence via reference to another patent's figure, which may not directly describe the accused product's operation.
    • Technical Questions: The claim recites a "sampler" and separate "signal converters." A potential issue is whether the accused product's integrated pipelined SAR architecture contains components that map directly onto this claimed structure, or if the functions are performed in a manner that is technically distinct from the claimed arrangement.

U.S. Patent No. 7,663,518 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a conversion engine comprising a switched capacitor array having redundancy The accused converters have a 13-bit, 3-stage pipelined SAR architecture, where each stage has 5 bits, thereby providing redundancy. ¶43 col. 2:50-52
a dither device for applying a dither to the conversion engine The first and second stages in a sub-ADC slice use "dithering injecting capacitors" to apply dither to the conversion engine. A diagram from a Xilinx presentation shows capacitors for "DTR INJ" (Dither Injection). ¶45 col. 2:55-57
a controller adapted to operate the conversion engine to perform a successive approximation conversion of an analog input The converters include a controller that provides control signals for each successive approximation register (SAR) stage in the sub-ADC slice. ¶46 col. 2:58-61
wherein the dither is removed from the conversion engine prior to completion of successive approximation bit trials as part of the analog-to-digital conversion The second and third stages in the sub-ADC slice use "dithering removing capacitors" to remove dither before the conversion is complete. A diagram from a Xilinx presentation shows capacitors for "DTR REM" (Dither Removal). ¶47 col. 2:62-66
  • Identified Points of Contention:
    • Scope Questions: The definition of "redundancy" will be a key issue for construction. The complaint asserts that using three 5-bit stages to produce a 13-bit output constitutes redundancy. The court will need to determine if this architecture meets the claimed requirement.
    • Technical Questions: The claim requires dither to be "removed... prior to completion of successive approximation bit trials." The central technical question will be what evidence demonstrates that the accused "dithering removing capacitors" operate at the specific time and in the specific manner required by this limitation. The complaint's visual evidence from a presentation slide depicts capacitors labeled "DTR REM," which may support the allegation that a dither removal mechanism exists (Compl. p. 17).

V. Key Claim Terms for Construction

  • Term: "aligner/corrector" (from ’452 Patent, claim 1)

    • Context and Importance: This term defines the digital back-end logic responsible for processing the raw outputs of the converter stages into a final, corrected code. The infringement analysis for the ’452 patent may turn on whether the accused product's digital logic performs the specific function of creating a "combined digital code" with distinct portions for the signal and the dither, as recited in the claim.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification uses broad, functional language, referring to this element as "digital correction logic 22" which "receives the digital outputs of the stages 20 and combines them to provide a final digital output" (’452 Patent, col. 3:9-12). This could support a construction covering any logic that combines and corrects stage outputs.
      • Evidence for a Narrower Interpretation: The primary embodiment shown in Figure 2 depicts the aligner/corrector 22 as a specific block that receives outputs from multiple distinct pipeline stages (20-1, 20-2, 20-3). A defendant may argue that the term should be construed in this more specific context of multi-stage pipeline error correction.

  • Term: "removed from the conversion engine prior to completion of successive approximation bit trials" (from ’518 Patent, claim 1)

    • Context and Importance: This limitation is the point of novelty for the ’518 Patent, distinguishing it from methods where dither is removed digitally after conversion. Infringement hinges on the timing and method of dither removal in the accused product. Practitioners may focus on this term because the allegation of an analog-domain removal mechanism is central to the infringement theory for this patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim uses functional language ("removed from the conversion engine"), which could be interpreted to cover any process that nullifies the dither's effect on the final bit decisions before the conversion process is fully complete, regardless of the specific circuit implementation.
      • Evidence for a Narrower Interpretation: The specification describes a specific embodiment where the dither is removed by connecting "a dither-removing DAC... to the main DAC" which "subtracts out the dither signal" in the analog domain during the conversion process (’518 Patent, col. 3:1-10; Fig. 2). A party could argue the term should be limited to such an active analog subtraction technique rather than a more passive capacitive effect.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges that Defendant induces infringement by providing its customers with manuals and product documentation that instruct them to use the Accused RFSoC Products in an infringing manner (e.g., Compl. ¶38, ¶48, ¶57, ¶67, ¶79, ¶90, ¶99, ¶107).
  • Willful Infringement: Willfulness is alleged for seven of the eight patents based on pre-suit knowledge stemming from claim charts Plaintiff allegedly provided to Defendant on July 31, 2019 (e.g., Compl. ¶39, ¶49). For the ’075 patent, the allegation is based on knowledge "since at least the filing of this complaint," suggesting a theory of post-suit willfulness (Compl. ¶107).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Question of Dither Mechanics and Timing: Across several asserted patents ('452, '518, '075), the core allegations relate to the specific implementation of dither. A central evidentiary question will be one of functional implementation: does the accused product's use of a pseudo-random bit sequence, injecting capacitors, and removing capacitors perform the distinct and specific functions required by each patent's claims—such as digital subtraction after conversion ('452) versus analog removal before the final bit trials are complete ('518)?
  2. Question of Architectural Correspondence: The complaint maps concepts from the patent claims (e.g., "sampler" plus "signal converters," "converter cores," "aligner/corrector") onto diagrams of the accused integrated pipelined SAR architecture. A key legal and factual issue will be one of structural mapping: does the highly integrated architecture of the Accused RFSoC Products contain the discretely claimed functional blocks, or is there a fundamental mismatch between the patent claims' required structure and the accused device's actual operation?
  3. Impact of Post-Filing IPRs: The cancellation of asserted independent claims in multiple patents-in-suit via Inter Partes Review proceedings initiated after the complaint was filed presents a threshold issue of case viability. The analysis will likely focus on whether the remaining asserted dependent claims are coextensive with the cancelled independent claims or offer narrower, patentable distinctions that can be proven to be infringed by the accused products.