Burbank Tech LLC v. Abaco Systems Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Burbank Technologies LLC (Texas)
  • Defendant: Abaco Systems, Inc. (Delaware)
  • Plaintiff’s Counsel: Chong Law Firm PA
• Case Identification: 1:21-cv-01516, D. Del., 10/27/2021
• Venue Allegations: Plaintiff alleges venue is proper in the District of Delaware because Defendant is incorporated in Delaware and has allegedly committed acts of patent infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant infringes a patent related to a specific architecture for macro-cell flip-flops used in programmable logic devices.
• Technical Context: The technology concerns the design of integrated circuits, specifically programmable logic devices (PLDs), and methods for efficiently testing their internal components after manufacturing.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,687,864 - “Macro-cell flip-flop with scan-in input,” issued February 3, 2004

The Invention Explained

• Problem Addressed: The patent addresses the difficulty of testing complex programmable logic devices (PLDs). As PLDs grew more complex, providing direct external access to test every internal logic element (a "macro-cell") became impractical due to a limited number of input/output (I/O) pins. Conventional testing methods required additional, dedicated boundary scan registers, which added complexity and cost to the chip design (U.S. Patent No. 6,687,864, col. 1:46-57).
• The Patented Solution: The invention proposes a macro-cell flip-flop architecture that includes two distinct data inputs: a primary input for normal logical operations and a secondary "scan-in" input exclusively for testing. A control signal selects which input is passed to the flip-flop's storage element. This design allows the macro-cells to be linked together into a "scan chain," enabling test data to be shifted serially through the chip’s internal logic using only a few dedicated I/O pins, thereby improving testability without the overhead of older methods ('864 Patent, Abstract; col. 2:2-11; Fig. 5).
• Technical Importance: The described architecture aimed to provide an efficient, low-overhead method for ensuring the functional integrity of complex semiconductor devices post-fabrication ('864 Patent, col. 2:4-11).

Key Claims at a Glance

• The complaint states it asserts "Exemplary '864 Patent Claims" detailed in an exhibit, but does not identify specific claims in the body of the complaint (Compl. ¶11). Independent claim 1 is representative of the core invention.
• Independent Claim 1:
  • A programmable logic device having a macro-cell comprising:
  • a multiplexer circuit configured to present (i) a first input as an output in response to a first state of a first control signal and (ii) a second input as said output in response to a second state of said first control signal; and
  • a flip-flop circuit configured to store said output in response to a clock signal.
• The complaint does not explicitly reserve the right to assert dependent claims, but generally alleges infringement of "one or more claims" (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

The complaint does not name any specific accused products. It refers generally to "Exemplary Defendant Products" that are identified in claim charts located in "Exhibit 2" (Compl. ¶¶11, 13). This exhibit was not filed with the complaint.

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context. It makes a conclusory allegation that the "Exemplary Defendant Products practice the technology claimed by the '864 Patent" (Compl. ¶13). It also alleges that Defendant's employees internally test and use these products (Compl. ¶12).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint incorporates infringement allegations by reference to an external document, "Exhibit 2," which is not publicly available (Compl. ¶¶13-14). The complaint itself contains no specific factual allegations mapping elements of any patent claim to features of any accused product. Therefore, a claim chart summary cannot be constructed.

• Identified Points of Contention: Lacking specific infringement contentions, the central dispute will likely revolve around fundamental architectural questions.
  • Architectural Questions: A primary question will be whether the accused products contain a circuit structure that can be characterized as a "multiplexer circuit" that selects between two functionally distinct inputs—one for normal operation and one for scan-based testing—as required by claim 1.
  • Technical Questions: The case may turn on whether the accused products implement a dedicated "control signal" for switching between normal and test modes, or if this functionality is achieved through a different mechanism not contemplated by the patent. Evidence will be needed to show that the accused devices "store" the selected input in a "flip-flop circuit" as claimed.

V. Key Claim Terms for Construction

Term: "multiplexer circuit"

• Context and Importance: This term is the structural heart of claim 1. The infringement analysis will depend on whether the accused products contain a structure that meets this definition. Practitioners may focus on this term because its scope—whether it is limited to the specific CMOS switch-based embodiments in the specification or can be read more broadly to cover any functionally equivalent selection logic—will be critical.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim uses the general term "multiplexer circuit" without structural limitations, suggesting any circuit that performs the claimed selection function could be covered ('864 Patent, col. 10:37-41).
  • Evidence for a Narrower Interpretation: The specification discloses a specific implementation of the multiplexer circuit comprising a series of transistors (M1-M7) and gates ('864 Patent, Fig. 4; col. 4:14-46). A defendant may argue that the term should be limited to this or structurally similar embodiments.

Term: "first input" / "second input"

• Context and Importance: The claim requires two distinct inputs selected by a control signal. The patent consistently describes the "first input" as a data signal for normal operation (e.g., "XORIN") and the "second input" as a test signal for scan-chain testing (e.g., "SCANIN") ('864 Patent, col. 2:57-61). The viability of the infringement claim may hinge on whether the accused products maintain this functional separation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim itself does not explicitly label the inputs as "data" and "test." It only requires two distinct inputs selected by a control signal, which a plaintiff might argue covers any two selectable data paths into a flip-flop.
  • Evidence for a Narrower Interpretation: The specification, including the "Summary of the Invention," consistently frames the invention as a solution for providing a "test mode" input separate from a "normal mode" input ('864 Patent, col. 1:60-65). Dependent claims reinforce this distinction, with claim 3 specifying the "first input comprises a data signal" and claim 6 specifying the "second input comprises a test signal" ('864 Patent, col. 10:48, 56-57).

VI. Other Allegations

Willful Infringement

The complaint does not contain factual allegations to support a claim for willful infringement, such as allegations of pre-suit knowledge of the patent or egregious conduct. The prayer for relief requests damages under 35 U.S.C. § 284, which allows for enhancement, and also asks that the case be declared "exceptional" for the purpose of awarding attorney fees under 35 U.S.C. § 285 (Compl. p. 4, ¶¶ D, E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Sufficiency: A threshold issue is whether the Plaintiff can produce evidence identifying the specific architecture of the accused products and demonstrate how that architecture aligns with the patent's claims, given the absence of such detail in the initial complaint.
2. Claim Scope and Definition: The case will likely turn on a question of definitional scope: will the term "multiplexer circuit" be construed broadly to cover any logic that performs a selection function, or will it be limited to the specific transistor-level implementations disclosed in the patent?
3. Functional Equivalence: A key question will be one of functional distinction: do the accused products possess a circuit that selects between a "normal" data input and a separate "test" scan input, as consistently described in the patent, or do they employ a more integrated or fundamentally different method for device testing that falls outside the claimed architecture?