DCT
1:22-cv-00174
Polaris Innovations Ltd v. Xilinx Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Polaris Innovations Limited (Ireland)
- Defendant: Xilinx, Inc. (Delaware)
- Plaintiff’s Counsel: Bayard, P.A.; Freitas & Weinberg LLP
- Case Identification: 1:22-cv-00174, D. Del., 02/08/2022
- Venue Allegations: Venue is alleged to be proper as Defendant is a Delaware corporation subject to personal jurisdiction in the district, where a substantial part of the events giving rise to the claims allegedly occurred.
- Core Dispute: Plaintiff alleges that Defendant’s Field-Programmable Gate Array (FPGA) and System on a Chip (SoC) products infringe four patents related to semiconductor memory initialization, output driver control, settable termination resistance, and circuit testing methods.
- Technical Context: The dispute centers on core functionalities within modern FPGAs and SoCs, specifically how these highly configurable chips interface with external high-speed memory like DDR SDRAM, a critical function for their widespread use in data centers, communications, and automotive systems.
- Key Procedural History: The complaint alleges that Plaintiff put Defendant on notice of infringement for the '589 and '369 patents on October 25, 2016, and for the '523 and '473 patents on December 7, 2016. These allegations of pre-suit knowledge form the basis for the claims of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 1998-06-30 | '589 Patent Priority Date |
| 2000-01-26 | '473 Patent Priority Date |
| 2000-12-05 | '589 Patent Issue Date |
| 2003-07-12 | '369 Patent Priority Date |
| 2004-03-02 | '473 Patent Issue Date |
| 2005-07-29 | '523 Patent Priority Date |
| 2006-12-05 | '369 Patent Issue Date |
| 2009-05-12 | '523 Patent Issue Date |
| 2016-10-25 | Alleged notice of infringement for '589 and '369 Patents |
| 2016-12-07 | Alleged notice of infringement for '523 and '473 Patents |
| 2022-02-08 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,157,589 - "Dynamic semiconductor memory device and method for initializing a dynamic semiconductor memory device," issued December 5, 2000
The Invention Explained
- Problem Addressed: During the power-up sequence of SDRAM memory, the internal control circuits can be in an unpredictable state, creating a risk of "bus contention" (a short circuit on data lines) or uncontrolled activation of internal current loads before the device is stable ('589 Patent, col. 1:21-34).
- The Patented Solution: The patent describes an initialization circuit that ensures a safe power-up. It waits for the supply voltage to stabilize and then requires a specific, predetermined sequence of external commands (e.g., a precharge command followed by refresh commands) to be received. Only after this proper sequence is identified does the circuit generate an "enable signal" (CHIPREADY) that unlatches the main control circuits, allowing for normal operation ('589 Patent, Abstract; col. 2:21-28).
- Technical Importance: This method provides a robust and reliable power-on-reset procedure for standardized memory, preventing electrical damage and ensuring the memory component enters a known, stable state before use ('589 Patent, col. 1:21-34).
Key Claims at a Glance
- The complaint asserts independent method claim 11 and dependent claims 12 and 13 (Compl. ¶22).
- Independent Claim 11 requires the essential steps of:
- Supplying a "supply voltage stable signal" via an initialization circuit.
- Supplying an "enable signal" via an enable circuit after identifying a "predetermined proper initialization sequence" of command signals.
- The enable signal "effecting an unlatching of a control circuit."
- Providing specific command signals as part of the sequence.
- "maintaining a latched condition of output drivers" during the switching-on operation until the enable signal is generated.
U.S. Patent No. 7,145,369 - "Output Driver For An Integrated Circuit And Method For Driving An Output Driver," issued December 5, 2006
The Invention Explained
- Problem Addressed: Output drivers on integrated circuits consume significant power, and their performance can vary due to manufacturing process fluctuations, temperature changes, and different electrical loads. Driving signals with more strength than necessary wastes power, while driving with too little strength can compromise signal integrity ('369 Patent, col. 1:40-67).
- The Patented Solution: The invention is an output driver with a feedback mechanism. It includes a measuring circuit to monitor the actual current or voltage on the output line. A control unit compares this measured value to a specified range and adjusts the "driver strength" accordingly. This allows the driver to operate in a "desired power range"—specifically a lower-power portion of the acceptable specification—thereby reducing power consumption while still ensuring reliable signaling ('369 Patent, Abstract; col. 2:15-24).
- Technical Importance: The technology enables dynamic, real-time optimization of I/O power consumption, a critical feature for high-speed, power-sensitive devices where balancing signal integrity and energy efficiency is paramount ('369 Patent, col. 2:63-67).
Key Claims at a Glance
- The complaint asserts dependent claim 2 and alleges contributory infringement of independent claim 1 (Compl. ¶¶32, 39).
- Independent Claim 1 requires an output driver comprising:
- A "driver circuit" for driving a signal onto an output line.
- A "measuring circuit" for measuring the output line current or potential.
- A "control unit" that sets the driver strength to operate in a "desired power range" of a specification.
- The control unit includes a "feedback control" that affects driver strength based on the measured value.
U.S. Patent No. 7,532,523 - "Memory Chip With Settable Termination Resistance Circuit," issued May 12, 2009
- Technology Synopsis: The patent addresses the problem of signal reflections on high-speed memory buses. It discloses a memory chip with an on-chip termination circuit whose resistance value can be dynamically changed as a function of received command signals (e.g., a different termination for a write operation versus a read operation). This allows for optimized signal integrity across different operating modes, which is an improvement over a single, fixed termination value ('523 Patent, Abstract; col. 1:45-54).
- Asserted Claims: Claims 5 and 6 (Compl. ¶43).
- Accused Features: The on-die termination (ODT) circuits in Xilinx products and their associated memory controllers. The complaint alleges these systems set termination resistance values (e.g., RZQ/4, RZQ/6) based on control commands (RAS#, CAS#) and mode register settings (Compl. ¶¶46-48). The complaint references an illustration of the memory bus connection between the accused product and DDR3 SDRAM (Compl. ¶49, citing Fig. 1-51 of the "Zynq-7000 AP SoC and 7 Series Device Memory Interface Solutions v.3.0 User Guide").
U.S. Patent No. 6,701,473 - "Electrical Circuit And Method For Testing A Circuit Component Of The Electrical Circuit," issued March 2, 2004
- Technology Synopsis: The patent describes a method for testing an individual component (e.g., a memory macro) on a complex chip without causing bus contention or excessive power draw. During the test, the component is configured to either output no data to the shared bus or to output data that is different from its normal operational data (e.g., static or infrequently changing data). This isolates the component for testing while ensuring the bus remains stable and power consumption is minimized ('473 Patent, Abstract; col. 2:5-15).
- Asserted Claims: Claims 11, 12, 13, 20, 26, 27, and 28 (Compl. ¶¶59, 66).
- Accused Features: The "write leveling" feature of the accused products' DDR3 SDRAM interface. The complaint alleges that during this test mode, the SDRAM is configured to output data that is "other than data which would be output to the bus during normal operation," for example, by outputting data on a DQ feedback line (Compl. ¶¶61-62). The complaint points to a depiction of this DQ feedback line as evidence (Compl. ¶62, citing Fig. 1-63 of the "Xilinx Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solution v3.0 User Guide").
III. The Accused Instrumentality
Product Identification
The accused products are Xilinx’s FPGAs and SoCs, including the Zynq Ultrascale+ MPSoC, Zynq-7000 SoC, UltraScale, 7-series, 6-series, Virtex-6, Virtex-5, and Spartan-6 product families (Compl. ¶¶18, 22). The infringement allegations center on products containing or programmed to implement a Dynamic Memory Interface compatible with DDR3, DDR3L, or DDR4 memory (Compl. ¶¶22, 32).
Functionality and Market Context
The accused products are described as semiconductor devices based on a matrix of configurable logic blocks and programmable interconnects, allowing them to be reprogrammed for various applications after manufacturing (Compl. ¶16). Certain products incorporate memory controllers, while others can be programmed to implement memory interface solutions using Xilinx's software tools (Compl. ¶20). The complaint asserts that Xilinx is the "industry leader" in FPGAs, which have "wide applicability" in numerous high-tech sectors (Compl. ¶¶15, 17).
IV. Analysis of Infringement Allegations
’589 Patent Infringement Allegations
| Claim Element (from Independent Claim 11) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| supplying, via the initialization circuit, a supply voltage stable signal once a supply voltage has been stabilized after the switching-on operation | The memory controllers supply a stable signal, such as the ddr_reset_n or RESET# signal, once the supply voltage has stabilized. |
¶23 | col. 2:19-22 |
| supplying, via an enable circuit of the initialization circuit, an enable signal...after an identification of a predetermined proper initialization sequence of the further command signals... | The controller supplies an enable signal, such as the ddr_cke signal, after an initialization sequence such as ZQ Calibration commands. |
¶23 | col. 2:22-26 |
| the enable signal effecting an unlatching of a control circuit provided for a proper operation of the dynamic semiconductor memory device | The enable signal allegedly effects an unlatching, indicated by the generation of VALID signals on the CKE, COMMAND, CA, and ODT lines. | ¶23 | col. 2:27-28 |
| providing at least one of a preparation command signal for word line activation, a refresh command signal, and a loading configuration register command signal as the further command signals | The controller provides the MRS command, which allegedly acts as both a preparation command and a loading configuration register command signal. | ¶24 | col. 2:50-54 |
| maintaining a latched condition of output drivers of the dynamic semiconductor memory device during the switching-on operation until the enable signal is generated | The controller maintains a latched condition, allegedly "as seen in the state of the RTT line during the switching-on operation." | ¶25 | col. 6:60-65 |
- Identified Points of Contention:
- Scope Questions: A primary question will be whether the specific signals from a modern DDR interface (e.g.,
ddr_cke,RESET#) correspond to the more general functional terms in the claims (e.g., "enable signal," "supply voltage stable signal"). - Technical Questions: The allegation that the "state of the RTT line" satisfies the "maintaining a latched condition of output drivers" limitation may be a key point of dispute. The court will need to determine if a circuit state for setting termination impedance is technically equivalent to the "latched condition" of the output drivers as described in the patent, which is intended to prevent bus contention ('589 Patent, col. 1:26-29).
- Scope Questions: A primary question will be whether the specific signals from a modern DDR interface (e.g.,
’369 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a driver circuit for driving an input signal of the output driver onto an output line | The accused products include a driver circuit, such as the VRN and VRP circuits, that drive a signal onto an output line. | ¶33 | col. 5:9-11 |
| a measuring circuit for measuring at least one of an output line current and an output line potential | The accused products contain a measuring circuit, such as the VRN and VRP circuits, that measures the potential of their outputs. | ¶34 | col. 5:15-18 |
| a control unit for providing a control signal for setting a driver strength of the driver circuit to provide at least one of the output line potential and the output line current in a desired power range... | The accused products contain a control unit, such as the DCI state machine, that controls the drive strength of the DDR IOB to provide an output potential in a desired power range. | ¶35 | col. 5:18-24 |
| wherein the control unit includes a feedback control to affect the setting of the driver strength based on a measured value provided by the measuring circuit | The control unit allegedly performs feedback control by adjusting VRN relative to VREF based on the measured value from the measuring circuit. | ¶35 | col. 8:1-3 |
- Identified Points of Contention:
- Scope Questions: The case may turn on whether the function of Xilinx's Digitally Controlled Impedance (DCI) technology, which is designed for impedance matching to maintain signal integrity, falls within the scope of the claimed "control unit" for setting driver strength within a "desired power range."
- Technical Questions: A factual dispute may arise over whether the alleged adjustment of "VRN relative to VREF" constitutes the "feedback control based on a measured value" as claimed, or if it is part of a different, unrelated calibration or impedance matching function.
V. Key Claim Terms for Construction
For the '589 Patent
- The Term: "latched condition of output drivers" (Claim 11)
- Context and Importance: This term is critical because the complaint's theory hinges on mapping it to the "state of the RTT line" in the accused products (Compl. ¶25). Practitioners may focus on this term because the RTT (Round Trip Time) line is typically associated with on-die termination (ODT) impedance calibration, not directly with latching the primary data output drivers in a high-impedance state. The defense is likely to argue these are distinct technical functions.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's background describes the problem to be solved as preventing "undesirable activation of output transistors" and "bus contention" ('589 Patent, col. 1:26-29). This could support a functional interpretation where any circuit state that prevents destructive bus conditions during power-up qualifies as a "latched condition."
- Evidence for a Narrower Interpretation: The specification suggests the output drivers are "held at high impedance" ('589 Patent, col. 2:44-45). This could support a narrower definition requiring the drivers to be in a specific high-impedance state, rather than simply having their termination impedance controlled via the RTT line.
For the '369 Patent
- The Term: "desired power range" (Claim 1)
- Context and Importance: This term is the core of the invention's power-saving objective. The infringement allegation relies on equating this with a potential range described in a Xilinx technical manual (Compl. ¶35). Practitioners may focus on this term because the accused DCI feature's primary purpose is impedance matching for signal integrity, not necessarily operation within a "power range."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states an objective is to "reduce the power consumption of the integrated circuit" ('369 Patent, col. 2:1-2). This might support construing any operational range that results in lower power as a "desired power range."
- Evidence for a Narrower Interpretation: Dependent claim 4 defines the "desired power range" as corresponding to a "lower portion" of the specification-prescribed potential and current ranges ('369 Patent, Claim 4). This suggests the term refers not to just any power reduction, but to a specific, defined sub-range of the overall specification limits.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement across all asserted patents, stating that Defendant encourages its customers to infringe by providing the products along with specifications, instructions, and user manuals that direct their infringing use (e.g., Compl. ¶¶26, 37, 53, 66). It also alleges contributory infringement, asserting that the accused products are key components, constitute material parts of the claimed inventions, are especially made for an infringing use, and have no substantial non-infringing uses (e.g., Compl. ¶¶28, 39, 55, 68).
- Willful Infringement: The complaint alleges willful infringement for all four patents based on pre-suit knowledge. It claims Defendant was put on notice of infringement of the '589 and '369 patents as of October 25, 2016 (Compl. ¶¶27, 38), and of the '523 and '473 patents as of December 7, 2016 (Compl. ¶¶54, 67). The complaint alleges that Defendant continued its infringing conduct despite this knowledge, acting in disregard of Plaintiff's patent rights (e.g., Compl. ¶¶30, 41, 57, 70).
VII. Analyst’s Conclusion: Key Questions for the Case
- 1. Technical Mapping: A central theme across all four patents will be one of technical translation: can the specific, documented operations of Xilinx's sophisticated memory interface circuits (e.g., the DCI state machine, the RTT line behavior, the write-leveling mode) be fairly mapped onto the functional language of the patent claims? The court will have to decide if these circuits inherently perform the functions recited in the claims, or if this represents a mismatch between the patented invention and the accused technology.
- 2. Functional Interpretation: For circuits with multiple purposes, such as Xilinx's Digitally Controlled Impedance (DCI) system, a key question will be one of primary versus incidental function. Does the DCI system, which is primarily for impedance matching, also perform the specific function of setting driver strength to operate in a "desired power range" as required by the '369 patent, or is any power-related effect merely an incidental byproduct of its main signal-integrity function?
- 3. Willfulness: Given the specific dates of alleged pre-suit notice, nearly six years before the complaint was filed, the willfulness claims will be a significant battleground. A key question for the court will be what actions, if any, Defendant took in response to the notice letters, and whether its continued sale of the accused products constituted objective recklessness in the face of a known risk of infringement.