Corrigent Corporation v. Arista Networks, Inc.

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Corrigent Corporation (Delaware) and Nahum Communication N.T.B Ltd. (Israel)
  • Defendant: Arista Networks, Inc. (Delaware)
  • Plaintiff’s Counsel: Steptoe LLP; Ashby & Geddes
• Case Identification: 1:22-cv-00497, D. Del., 08/16/2024
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is a Delaware corporation and therefore resides in the district.
• Core Dispute: Plaintiffs allege that Defendant’s 7500R Series Switches infringe two patents related to hidden failure detection in modular systems and MAC address learning in distributed network bridges.
• Technical Context: The technologies at issue relate to reliability and performance in high-capacity network switches, which form the backbone of modern data centers and telecommunications networks.
• Key Procedural History: The First Amended Complaint was filed on August 16, 2024, following an original complaint filed on April 19, 2022. The complaint alleges Defendant has had knowledge of the patents-in-suit since at least the date of the original filing.

Case Timeline

Date	Event
1990-01-01	Corrigent-Systems founded
1996-01-01	Corrigent-Systems listed on Nasdaq Stock Exchange
2000-01-01	Corrigent-Systems began developing Ethernet products
2002-05-30	Earliest Priority Date for ’369 Patent
2005-01-01	KDDI deployed Corrigent-Systems Ethernet switch products
2005-10-18	’369 Patent Issued
2006-05-19	Earliest Priority Date for ’400 Patent
2009-09-22	’400 Patent Issued
2022-04-19	Original Complaint Filed
2024-08-16	First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,957,369 - "HIDDEN FAILURE DETECTION," issued October 18, 2005

The Invention Explained

• Problem Addressed: The patent addresses "hidden failures," where idle components or communication lines in an electronic system fail but the failure goes undetected because the component is not in active use. This problem is particularly troublesome as the failure only becomes apparent when the component is needed for service, causing an outage (ʼ369 Patent, col. 1:11-20).
• The Patented Solution: The invention proposes a non-intrusive self-testing method that uses the system's existing components without dedicated test hardware. The method selects an idle communication line to serve as an "aid trace" and instructs the module at its end to loop back any traffic it receives. It then selects a second idle line for testing and configures the system's main switch to link the test trace to the aid trace. The module on the test trace sends test traffic, which travels through the switch to the aid trace, is looped back, and should return to the sending module. If the traffic does not return correctly, a hidden failure is detected and reported (ʼ369 Patent, Abstract; col. 2:6-23). The complaint reproduces a block diagram from the patent illustrating the modular system architecture (Compl. p. 6, citing ’369 Patent, Fig. 1).
• Technical Importance: This approach allows for proactive maintenance in high-availability systems by detecting latent faults on backup or idle lines without interrupting live traffic on active lines (ʼ369 Patent, col. 2:26-29).

Key Claims at a Glance

• The complaint asserts independent claim 15 (Compl. ¶19, 31).
• The essential elements of claim 15 for a "Modular electronic apparatus" are:
  • A backplane with traces for carrying data between modules.
  • A main module with a switch having ports connected to the backplane traces.
  • At least first and second subsidiary modules connected via the traces, where some traces are sometimes idle.
  • A system control processor operative to:
    • Select a first idle trace (connected to the first subsidiary module) as an "aid trace."
    • Instruct the first subsidiary module to loop back traffic from the aid trace.
    • Select a second idle trace (connected to the second subsidiary module) for testing.
    • Configure the switch to link the first and second ports corresponding to the aid and test traces.
    • Cause test traffic to be sent from the second subsidiary module over the test trace, through the switch, to the aid trace.
    • Report a failure if the test traffic does not return to the second subsidiary module within a set time.
• The complaint does not explicitly reserve the right to assert other claims.

U.S. Patent No. 7,593,400 - "MAC ADDRESS LEARNING IN A DISTRIBUTED BRIDGE," issued September 22, 2009

The Invention Explained

• Problem Addressed: The patent addresses challenges in Media Access Control (MAC) address learning within "distributed bridging systems," such as Virtual Private LAN Services (VPLS), where multiple physical line cards or nodes must act as a single, coherent Layer 2 bridge (’400 Patent, col. 1:6-9). Keeping the forwarding databases (FDBs) on each card synchronized is critical for correct and efficient operation.
• The Patented Solution: The invention provides an improved method for distributed MAC learning. When a data packet with a previously unknown source MAC address arrives at an ingress port on a line card, that card creates a new entry in its local FDB. Crucially, it also sends a "message of the association" to the other "member line cards" in the distributed bridge. This synchronization message allows all member cards to add the new MAC address-to-port association to their respective FDBs, ensuring consistent forwarding decisions across the entire logical bridge (’400 Patent, Abstract; col. 7:3-25). The complaint provides a flowchart from the patent that illustrates this MAC learning and synchronization process (Compl. p. 8, citing ’400 Patent, Fig. 3).
• Technical Importance: This method facilitates consistent and efficient MAC learning in complex network environments, particularly those using Link Aggregation (LAG) where multiple physical ports are treated as a single logical link, preventing unnecessary traffic flooding and ensuring proper packet forwarding (’400 Patent, col. 2:60-3:2).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶24, 39).
• The essential elements of claim 1, a "method for communication," are:
  • Configuring a network node (with multiple line cards and ports) to act as a distributed MAC bridge.
  • Configuring a Link Aggregation (LAG) group of parallel physical links.
  • Providing each member line card with its own forwarding database (FDB).
  • Receiving a data packet with a source MAC address on an ingress port.
  • Conveying the packet toward its destination.
  • If the destination MAC is unknown, flooding the packet via only one LAG port.
  • Checking the source MAC against the FDB of the first line card.
  • If the source MAC association is not in the FDB, creating a new record, adding it to the FDB, and "sending a message of the association to each member line card" of the LAG.
• The complaint does not explicitly reserve the right to assert other claims.

III. The Accused Instrumentality

Product Identification

• The complaint identifies the "Arista 7500R Series Switches" as the Accused Products (Compl. ¶27).

Functionality and Market Context

• The complaint describes the Accused Products as networking hardware, including routers and switches, used in data centers (Compl. ¶26, 29). It alleges these products are modular systems that incorporate the claimed technologies. The complaint cites Arista's own technical documents, such as the "Arista 7500R Switch Architecture" whitepaper and user manuals, as evidence that the products perform functions related to the subject matter of the asserted patents (Compl. ¶29). The complaint does not, however, provide specific details on the operational mechanics of the accused features, instead incorporating by reference external exhibits that were not filed with the complaint (Compl. ¶29, 31, 39).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits for its infringement allegations but does not include them in the filing (Compl. ¶29, 31, 39). The narrative infringement theory is summarized below.

• ’369 Patent Infringement Allegations: The complaint alleges that the Arista 7500R Series Switches infringe at least claim 15 (Compl. ¶31). The implicit theory is that these modular switches contain a backplane, a main module, subsidiary modules (line cards), and a control processor. The infringement allegation rests on the premise that these switches execute a non-intrusive self-test procedure on idle communication traces that corresponds to the specific sequence of selecting an aid trace, looping back traffic, and reporting failures as recited in the claim (Compl. ¶19, 31). The complaint does not provide specific factual allegations detailing how the Accused Products perform this claimed method.
• ’400 Patent Infringement Allegations: The complaint alleges that the Arista 7500R Series Switches infringe at least claim 1 (Compl. ¶39). The narrative theory is that the accused switches operate as distributed bridges, support LAG groups, and implement a MAC address learning protocol that meets the claim limitations. This includes maintaining per-line-card FDBs and, crucially, propagating newly learned MAC address associations from one line card to other member line cards via a "message" to ensure FDB synchronization across the distributed system (Compl. ¶24, 39). The complaint does not specify the exact mechanism by which this alleged synchronization occurs in the Accused Products.
• Identified Points of Contention:
  • Factual Questions: A primary point of contention will be factual: can Plaintiffs produce evidence that the Arista 7500R Series Switches actually perform the specific functions claimed? For the ’369 Patent, this raises the question of whether Arista's hardware diagnostics implement the claimed loopback test method. For the ’400 Patent, it raises the question of how Arista's proprietary Extensible Operating System (EOS) synchronizes MAC tables across line cards in a LAG group.
  • Scope Questions: The infringement analysis for the ’400 Patent may turn on the scope of the phrase "sending a message of the association." What evidence will show that Arista's internal synchronization process qualifies as a "message" sent to "each member line card" as required by the claim, versus a different architecture for database consistency?

V. Key Claim Terms for Construction

• Term from ’369 Patent, Claim 15: "system control processor"

  • Context and Importance: This term defines the entity that orchestrates the entire patented test method. The infringement analysis will depend on whether the functions recited for this processor are performed by a single, identifiable component in the Arista switches or by a distributed set of processors. Practitioners may focus on this term because modern, complex switches often use a distributed control plane, which may not map cleanly to the "system control processor" architecture described in the patent.
  • Intrinsic Evidence for a Broader Interpretation: The specification describes subsidiary modules as also having their own processors ("subsidiary processors 44"), suggesting the "system control processor" may be a logical role that directs other processors rather than a single physical chip that performs every action itself (ʼ369 Patent, col. 5:44-45, Fig. 1).
  • Intrinsic Evidence for a Narrower Interpretation: The primary embodiment describes a distinct "system control processor 42 in main module 22" that supervises the test procedure (ʼ369 Patent, col. 5:41-43). The figures likewise depict a single CPU (42) in the main module, which could support an argument that the term requires a centralized controller.

• Term from ’400 Patent, Claim 1: "sending a message of the association to each member line card"

  • Context and Importance: This limitation is the core of the claimed FDB synchronization mechanism. The case may hinge on whether Arista's method for propagating MAC learning constitutes "sending a message."
  • Intrinsic Evidence for a Broader Interpretation: Parties may argue that any protocol that effectively transmits the association data from a learning card to other member cards constitutes "sending a message," regardless of the specific format or transport mechanism.
  • Intrinsic Evidence for a Narrower Interpretation: The specification includes a flowchart that shows a discrete "SEND SYNCUPDATE" step (ʼ400 Patent, Fig. 3, element 82). This may support an argument that the claim requires a specific, distinct message packet for synchronization, rather than another form of inter-process communication or shared memory update within the switch chassis.

VI. Other Allegations

• Indirect Infringement: The complaint alleges active inducement of infringement for both patents. This is based on allegations that Defendant's marketing materials, datasheets, user manuals, and other guides instruct and encourage customers to use the Accused Products in a manner that directly infringes the patents (Compl. ¶33, 41).
• Willful Infringement: The complaint does not use the term "willful," but it lays the groundwork for alleging post-suit willful infringement. It alleges that Defendant has had knowledge of both patents "at least as of the filing of the Complaint (D.I. 1) on April 19, 2022" and that it "continues to induce" infringement by its customers despite this knowledge (Compl. ¶32, 40).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of evidentiary sufficiency: Given that the complaint's infringement allegations rely on external exhibits that were not provided, a key question is whether Plaintiffs can produce, through discovery, concrete technical evidence that the Accused Products' actual diagnostic and MAC learning functions perform the specific steps recited in the asserted claims.
• The case may turn on a question of technical and legal scope: For the ’400 Patent, does Arista's proprietary method for ensuring FDB consistency across line cards in a distributed switch constitute "sending a message of the association to each member line card" as that phrase would be construed by the court, or is it a fundamentally different technical approach to synchronization?
• A key claim construction question for the ’369 Patent will be one of architectural mapping: Can the functions of the claimed "system control processor," described in the context of a 2002-era design, be mapped onto the potentially more distributed control plane architecture of the modern Arista 7500R switches, or is there a dispositive mismatch between the claimed and accused architectures?