Mallard IP LLC v. Broadberry Data Systems LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mallard IP LLC (Texas)
  • Defendant: Source Code, LLC dba Broadberry Data Systems LLC (Delaware)
  • Plaintiff’s Counsel: Chong Law Firm; Kent & Risley LLC
• Case Identification: 1:22-cv-00568, D. Del., 06/09/2022
• Venue Allegations: Venue is asserted on the basis that the Defendant is a Delaware corporation and therefore resides in the judicial district.
• Core Dispute: Plaintiff alleges that Defendant’s server products infringe a patent related to dynamically configurable digital circuit architectures.
• Technical Context: The technology concerns programmable circuit blocks designed for efficiency and dynamic reconfiguration, distinguishing them from general-purpose Field Programmable Gate Arrays (FPGAs).
• Key Procedural History: The patent-in-suit was originally assigned to Cypress Semiconductor Corporation. The complaint does not mention any prior litigation or administrative proceedings involving the patent.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,603,330 - "Configuring Digital Functions in a Digital Configurable Macro Architecture"

• Patent Identification: U.S. Patent No. 6,603,330, "Configuring Digital Functions in a Digital Configurable Macro Architecture," issued August 5, 2003.

The Invention Explained

• Problem Addressed: The patent asserts that conventional Field Programmable Gate Arrays (FPGAs) are inefficient for many microcontroller applications due to high cost and underutilization of logic resources, and that re-programming them for new functions is a time-consuming task (’330 Patent, col. 1:46-57).
• The Patented Solution: The invention is a "programmable digital circuit block" architecture designed for reuse and efficiency. Unlike a generic FPGA that can be programmed for any arbitrary function, this block is designed to be dynamically configured to perform any one of a variety of predetermined digital functions (e.g., a timer, counter, or serial communication port) by changing the contents of a small number of configuration registers (’330 Patent, Abstract; col. 2:1-11). This allows for fast, on-the-fly reconfiguration for real-time processing (’330 Patent, col. 2:25-33). The architecture is illustrated in Figure 1, which shows configuration registers (50) controlling selectable logic circuits (30) via a system bus (90) (’330 Patent, Fig. 1).
• Technical Importance: The described approach sought to provide the flexibility of programmable logic while improving the cost and area efficiency for common, well-defined functions frequently required in microcontroller designs (’330 Patent, col. 4:56-65).

Key Claims at a Glance

• The complaint asserts at least independent claim 25 (Compl. ¶16).
• Claim 25 is a method claim with the following essential steps:
  • "a) loading a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions into a configuration register of said programmable digital circuit block; and"
  • "b) configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data,"
  • "wherein said steps a) and b) are dynamically performed, and"
  • "wherein said programmable digital circuit block includes a data register for storing data to facilitate performing any one of said plurality of predetermined digital functions."
• The complaint does not explicitly reserve the right to assert other claims.

III. The Accused Instrumentality

Product Identification

• Defendant's "CyberServe EPYC EP1-102" (Compl. ¶16).

Functionality and Market Context

• The complaint identifies the accused instrumentality by its product name but does not provide any specific technical details about its architecture, components, or operation (Compl. ¶16). The name suggests it is a server-class computer system. The complaint alleges the defendant makes, uses, sells, offers for sale, and/or imports the accused product (Compl. ¶14). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges infringement of at least claim 25 and states that the allegations are "detailed in the preliminary claim chart attached hereto as Exhibit B" (Compl. ¶16). As this exhibit was not included with the filed complaint provided for analysis, a detailed claim chart summary cannot be constructed. The complaint’s narrative theory is that the Defendant’s "CyberServe EPYC EP1-102" product infringes, either literally or under the doctrine of equivalents (Compl. ¶16).

• Identified Points of Contention:
  • Evidentiary Question: The complaint does not plead any specific facts explaining how the accused server performs the steps of the asserted method claim. A central issue will be what evidence demonstrates that the accused server "load[s] a plurality of configuration data" to "dynamically" configure a "programmable digital circuit block" to perform a "predetermined digital function," as required by claim 25.
  • Technical Question: Claim 25 is a method claim. The complaint accuses a product. The infringement allegation therefore appears to rest on the defendant's use of the CyberServe product in an infringing manner (Compl. ¶14-15). The court will need to determine if the operation of the server, or a component within it, practices the claimed method.
  • Scope Questions: The patent describes its invention in the context of microcontroller applications and distinguishes it from general-purpose FPGAs (’330 Patent, col. 1:22-30, 46-57). A question for the court may be whether the term "programmable digital circuit block," as used in the patent, can be construed to read on the architecture of a high-performance, general-purpose CPU (such as an AMD EPYC processor, as suggested by the product name) found in a modern server.

V. Key Claim Terms for Construction

• The Term: "predetermined digital functions"

• Context and Importance: This term appears central to distinguishing the invention from a generic, fully programmable device like an FPGA. Its construction will likely define the scope of infringing activities. Practitioners may focus on this term because the patent lists specific examples, such as timers, counters, PWMs, and communication ports, suggesting a finite and pre-selected set of operations (’330 Patent, col. 4:1-7). The infringement analysis will depend on whether the accused server can be shown to perform one of these types of functions using a dynamically configurable block.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claims use the open-ended phrase "a plurality of predetermined digital functions," which might be argued to encompass any function that is selectable from a pre-defined list, not just those explicitly enumerated in the specification.
  • Evidence for a Narrower Interpretation: The specification repeatedly lists a specific class of functions (timer, counter, PWM, CRC, UART, SPI) as examples of the "predetermined digital functions" (’330 Patent, col. 4:1-7; Claim 6). A party could argue the term is limited to this class of relatively simple, hardware-level functions common in microcontrollers, as opposed to high-level software operations.

• The Term: "programmable digital circuit block"

• Context and Importance: This is the apparatus being programmed in the asserted method claim. Its definition is critical, as the patent specification explicitly contrasts it with an FPGA (’330 Patent, col. 2:1-4). The case may turn on whether a component within the accused server meets this definition.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party might argue the term broadly covers any programmable logic that is not a traditional CPU, including reconfigurable sections of modern SoCs (Systems-on-a-Chip).
  • Evidence for a Narrower Interpretation: The patent describes the block as comprising specific, reused circuit components ("selectable logic circuits," "data registers") configured by dedicated "configuration registers" to minimize die area (’330 Patent, col. 4:56-65; Fig. 1). This could support a narrower construction limited to architectures with these specific structural features, as opposed to the more complex and general-purpose architecture of a server CPU.

VI. Other Allegations

• Indirect Infringement: The complaint makes general allegations of making, using, and selling the accused product, which primarily sound in direct infringement (Compl. ¶14-15). It does not plead specific facts to support claims of induced or contributory infringement, such as allegations of instructing others to infringe or providing a non-staple component for infringement.
• Willful Infringement: The complaint does not include a specific count for willful infringement or allege that Defendant had pre- or post-suit knowledge of the ’330 Patent. However, the prayer for relief requests that the court declare the case "exceptional" and award attorneys' fees pursuant to 35 U.S.C. § 285 (Compl., Prayer for Relief ¶D).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of technical applicability: can the patent’s claims, which describe a "programmable digital circuit block" for "predetermined digital functions" in the context of efficient microcontroller design, be applied to the architecture of a high-performance, general-purpose server product? The outcome may depend on whether the accused product contains a specific hardware component that maps onto the patent's teachings.
• A key threshold question will be one of evidentiary sufficiency: does the Plaintiff possess, and can it present, evidence to substantiate the conclusory allegation that the accused server practices the specific steps of method claim 25? The complaint itself provides no factual detail to connect the accused product to the claimed method, creating a significant burden for the Plaintiff to meet during discovery and claim construction.