DCT

1:22-cv-01292

Bell Semiconductor LLC v. Micron Technology Inc

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:22-cv-01292, D. Del., 12/16/2022
  • Venue Allegations: Venue is alleged to be proper as all defendants are Delaware corporations, making them residents of the district.
  • Core Dispute: Plaintiff alleges that semiconductor chips manufactured by Micron, and downstream products sold by the other defendants that incorporate these chips, infringe six patents related to semiconductor device structure, manufacturing methods, and packaging technologies.
  • Technical Context: The patents-in-suit relate to foundational aspects of semiconductor design and packaging, including techniques to reduce parasitic capacitance, improve thermal reliability, protect against electrostatic discharge, and isolate high-speed circuitry—all critical for the performance of modern electronics.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant Micron with actual notice of each asserted patent on various dates between February 2020 and December 2021, forming the basis for allegations of willful infringement.

Case Timeline

Date Event
2001-10-23 U.S. Patent 6,818,953 Priority Date
2003-10-08 U.S. Patent 7,345,245 Priority Date
2004-11-16 U.S. Patent 6,818,953 Issues
2005-09-21 U.S. Patent 8,319,343 Priority Date
2006-03-22 U.S. Patent 8,049,340 Priority Date
2006-03-22 U.S. Patent 8,288,269 Priority Date
2006-04-06 U.S. Patent 7,646,091 Priority Date
2008-03-18 U.S. Patent 7,345,245 Issues
2010-01-12 U.S. Patent 7,646,091 Issues
2011-11-01 U.S. Patent 8,049,340 Issues
2012-10-16 U.S. Patent 8,288,269 Issues
2012-11-27 U.S. Patent 8,319,343 Issues
2020-02-11 Plaintiff provides notice of '340 & '269 patents to Micron
2021-06-29 Plaintiff provides notice of '245 & '091 patents to Micron
2021-09-23 Plaintiff provides notice of '343 patent to Micron
2021-12-13 Plaintiff provides notice of '953 patent to Micron
2022-12-16 Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,049,340

  • Patent Identification: U.S. Patent No. 8,049,340, "Device for Avoiding Parasitic Capacitance in an Integrated Circuit Package," issued November 1, 2011.
  • The Invention Explained:
    • Problem Addressed: In high-speed integrated circuits, unintended electrical coupling, or "parasitic capacitance," can form between metal layers (such as signal routing layers and contact pads) that are in close proximity. This capacitance can distort the electrical signals, limiting the circuit's maximum operating frequency and performance (Compl. ¶31, citing '340 Patent, col. 2:52-60).
    • The Patented Solution: The invention proposes a specific structural modification to the package substrate to mitigate this problem. It teaches creating voids, or "cutouts," in the metal layers that are located directly above or below the electrical contact pads. These cutouts are designed to be the same size as or larger than the contacts, creating an insulating gap that "substantially" eliminates the physical overlap between the metal layers and the contacts, thereby reducing parasitic capacitance (Compl. ¶¶34-35). The patent specification explains this reduces distortion of high-frequency switching waveforms ('340 Patent, col. 3:21-25).
    • Technical Importance: By reducing parasitic capacitance, this design allows integrated circuits to operate reliably at higher frequencies, a critical factor for improving performance in devices like high-speed memory and processors (Compl. ¶36).
  • Key Claims at a Glance:
    • The complaint asserts independent claim 7 (Compl. ¶35).
    • The essential elements of independent claim 7 include:
      • An integrated circuit package substrate comprising a first layer with electrical contacts and a separate routing metal layer.
      • A dielectric layer situated between the first layer and the routing metal layer, with no intermediate conductive layer.
      • A plurality of "cutouts" formed in the routing metal layer specifically for reducing parasitic capacitance.
      • The cutouts must overlap the electrical contacts and be of the same or larger dimensions, such that there is "substantially no overlap" between the contact pads and the metal in the routing metal layer.
    • The complaint does not explicitly reserve the right to assert other claims for this patent, but standard practice allows for it.

U.S. Patent No. 8,288,269

  • Patent Identification: U.S. Patent No. 8,288,269, "Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package," issued October 16, 2012.
  • The Invention Explained:
    • Problem Addressed: The complaint states that the ’269 patent shares an identical specification with the '340 patent and is directed to the same problem: signal degradation in multi-layer packages caused by parasitic capacitance between electrical contacts and adjacent conductive layers (Compl. ¶39, referencing ¶31).
    • The Patented Solution: While the '340 patent claims the physical device structure, the ’269 Patent claims the method of manufacturing it. The invention is a fabrication process that involves forming a first conductive layer with contact pads, adding an insulating layer, and then forming a second conductive layer that incorporates "cutouts." These cutouts are positioned to completely overlap the underlying contact pads, ensuring "substantially no overlap" between the pad and the metal of the second layer (Compl. ¶¶39-40; ’269 Patent, Abstract).
    • Technical Importance: The claimed method enables the manufacture of semiconductor packages with inherently lower parasitic capacitance, which in turn allows for higher operating frequencies and improved device performance (Compl. ¶42).
  • Key Claims at a Glance:
    • The complaint asserts independent claim 1 (Compl. ¶40).
    • The essential elements of independent claim 1 include the steps of:
      • Forming a first electrically conductive layer with a plurality of rows of contact pads.
      • Forming an electrically insulating layer on the first layer.
      • Forming a second electrically conductive layer over the insulating layer, with no intermediate conductive layer between the first and second layers.
      • The second layer must comprise metal and a plurality of cutouts, where each cutout encloses an insulating area that "completely overlaps" a corresponding contact pad, resulting in "substantially no overlap" of the contact pads with the metal.
    • The complaint also recites dependent claim 6, which adds the limitations of forming the second layer as a routing layer and aligning the cutouts with the rows of contact pads (Compl. ¶41).

Multi-Patent Capsule: U.S. Patent No. 7,345,245

  • Patent Identification: U.S. Patent No. 7,345,245, "Robust High Density Substrate Design for Thermal Cycling Reliability," issued March 18, 2008 (Compl. ¶43).
  • Technology Synopsis: This patent addresses the problem of physical stress and cracking that occurs in semiconductor packages, particularly under the corners of the die, during thermal excursions. The patented solution improves reliability by defining a high-stress "keep-out" zone and routing signal traces away from the ball pads located within this area, thereby preventing cracks from propagating into the signal traces (Compl. ¶¶45-46).
  • Asserted Claims: The complaint recites independent claim 1 (Compl. ¶47).
  • Accused Features: The complaint accuses Micron's T15SB1 SSD Controller, as found in products like the Micron 2200 SSD (Compl. ¶94).

Multi-Patent Capsule: U.S. Patent No. 7,646,091

  • Patent Identification: U.S. Patent No. 7,646,091, "Semiconductor Package and Method Using Isolated Vss Plane to Accommodate High Speed Circuitry Ground Isolation," issued January 12, 2010 (Compl. ¶49).
  • Technology Synopsis: The patent addresses electrical noise, cross-talk, and "ground bounce" that arise when high-speed and low-speed circuits share a common ground plane. The invention solves this by creating a package structure with at least two distinct ground planes: one dedicated to the low-speed circuitry and a second, "spatially separated and electrically isolated" ground plane for the high-speed circuitry (Compl. ¶¶51-52).
  • Asserted Claims: The complaint recites independent claim 1 (Compl. ¶53).
  • Accused Features: The complaint accuses Micron's T15SB1 SSD Controller, as found in products like the Micron 2200 SSD (Compl. ¶104).

Multi-Patent Capsule: U.S. Patent No. 6,818,953

  • Patent Identification: U.S. Patent No. 6,818,953, "Protection of an integrated circuit against electrostatic discharges and other overvoltages," issued November 16, 2004 (Compl. ¶55).
  • Technology Synopsis: The patent targets the problem of bulky electrostatic discharge (ESD) protection circuits, which consumed significant chip area and hindered miniaturization. The invention provides a more space-efficient design by integrating the ESD protection switch directly into the supply rail, under the supply conductors, rather than adjacent to them (Compl. ¶¶57-58).
  • Asserted Claims: The complaint recites independent claim 1 (Compl. ¶59).
  • Accused Features: The complaint accuses Micron's MT41K512 M8RH 4GB DDR3 SDRAM as an exemplary infringing product (Compl. ¶124).

Multi-Patent Capsule: U.S. Patent No. 8,319,343

  • Patent Identification: U.S. Patent No. 8,319,343, "Routing Under Bond Pad for the Replacement of an Interconnect Layer," issued November 27, 2012 (Compl. ¶61).
  • Technology Synopsis: This patent addresses an inefficiency in conventional flip-chip manufacturing, which required an additional, costly interconnect metallization layer to link an aluminum alloy bond pad to underlying copper circuitry. The invention teaches a novel routing structure where the bond pad layer itself is segmented to serve as both the bond pad and an interconnect runner, thereby eliminating the need for the separate interconnect layer and its associated costs and processing steps (Compl. ¶¶63-64).
  • Asserted Claims: The complaint recites independent claim 1 (Compl. ¶65).
  • Accused Features: The complaint accuses Micron's T15SB1 SSD Controller, as found in products like the Micron 2200 SSD (Compl. ¶114).

III. The Accused Instrumentality

  • Product Identification: The complaint primarily accuses semiconductor devices manufactured by Defendant Micron Technology, Inc. These include specific product families such as GDDR5, GDDR6, and GDDR6X SGRAM; various SSD Controllers (e.g., T15SB1, DM02A1); and DDR3 SDRAM (Compl. ¶¶1-2). The complaint also accuses downstream products manufactured and sold by the other defendants (AMD, CDW, Dell, HP, NVIDIA), such as graphics cards, SSDs, and PCs, that incorporate the accused Micron components (Compl. ¶¶132, 141, 162).
  • Functionality and Market Context: The accused components are high-performance memory and storage controller chips that are fundamental to the operation of modern computing devices (Compl. ¶1). The complaint alleges that these Micron components are not trivial or non-essential, but rather that their performance characteristics are critical to enabling the high performance of the downstream products in which they are used, thus driving market demand (Compl. ¶¶84, 137).
    No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references exemplary claim charts (Exhibits G-L) for each asserted patent, but these exhibits were not attached to the filed complaint document. Consequently, the infringement allegations are summarized below based on the narrative infringement theories presented in the complaint.

  • '340 Patent Infringement Allegations: The complaint alleges that Micron's high-speed memory products, such as its GDDR6 SGRAM, directly infringe the '340 patent because their physical structure incorporates the claimed features (Compl. ¶70). The infringement theory posits that to achieve their high data rates, these devices necessarily employ a multi-layer package substrate with structures equivalent to the claimed "cutouts" to reduce parasitic capacitance between contact pads and other metal layers (Compl. ¶¶31, 36). Without the provided claim chart (Ex. G), a detailed element-by-element analysis is not possible.
  • '269 Patent Infringement Allegations: The complaint alleges infringement of the '269 patent under 35 U.S.C. § 271(g), which pertains to importing, selling, or using a product made by a patented process (Compl. ¶81). The theory is that the accused Micron SGRAM products are manufactured abroad using a process that meets the steps of the '269 method patent—specifically, by forming conductive and insulating layers with the claimed "cutouts" to minimize parasitic capacitance (Compl. ¶¶39, 82). The complaint further alleges these products are not materially changed by subsequent processes (Compl. ¶83). The claim chart (Ex. H) was not provided.
  • Identified Points of Contention:
    • Scope Questions: The infringement analysis for the '340 and '269 patents may turn on the construction of the phrase "substantially no overlap." The court will need to determine the permissible degree of overlap, if any, under this limitation. This raises the question of whether minor, incidental overlap due to manufacturing tolerances falls outside the claim scope.
    • Technical Questions: The complaint's allegations are made on "information and belief." A central evidentiary question for the court will be what proof the plaintiff can offer to demonstrate that the internal, microscopic structures of the accused semiconductor packages actually contain the claimed "cutouts" that "completely overlap" corresponding contact pads. This will likely require detailed reverse engineering and expert analysis.

V. Key Claim Terms for Construction

  • The Term: "substantially no overlap" (appearing in '340 Patent, Claim 7 and '269 Patent, Claim 1)

    • Context and Importance: This term is central to the invention's core concept of reducing parasitic capacitance. Its construction will directly impact the scope of infringement, as it defines the required degree of separation between the contact pads and surrounding metal. Practitioners may focus on this term because its ambiguity could be outcome-determinative.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A party might argue that "substantially" is a term of degree that does not require absolute or zero overlap, allowing for minor or insignificant overlaps that do not materially affect the device's function.
      • Evidence for a Narrower Interpretation: The patent specification repeatedly emphasizes the goal of avoiding parasitic capacitance caused by overlap ('340 Patent, col. 3:9-25). Furthermore, '269 patent claim 1 uses the phrase "completely overlaps" to describe the relationship between the insulating area in the cutout and the contact pad, which may suggest that "substantially no overlap" with the surrounding metal is intended to mean a near-total or complete lack of overlap. The patent's figures also depict a clear separation ('340 Patent, Fig. 5).

  • The Term: "cutout" (appearing in '340 Patent, Claim 7 and '269 Patent, Claim 1)

    • Context and Importance: The definition of "cutout" is critical for determining what constitutes an infringing structure. The question is whether any void in a metal layer qualifies, or if the term implies a feature specifically designed and shaped for the purpose of capacitance reduction.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A party could argue for the term's plain and ordinary meaning, covering any area from which conductive material has been removed or was intentionally not deposited, regardless of its specific shape or the designer's primary intent.
      • Evidence for a Narrower Interpretation: The claims themselves tie the cutout to a function: "for reducing parasitic capacitance" ('340 Patent, Claim 7). The specification describes the cutout as enclosing an area that "completely surrounds the contact pad" ('340 Patent, col. 4:4-8). This language suggests that a "cutout" is not a random void but a purposefully engineered feature with a specific geometry and function relative to the contact pad.

VI. Other Allegations

  • Indirect Infringement: The complaint states that "Only direct infringement of the Asserted Patents by Defendants is presently at issue," and explicitly reserves the right to pursue indirect infringement claims later (Compl. ¶3, fn. 1). The counts against downstream defendants such as AMD and Dell are pleaded as direct infringement under 35 U.S.C. §§ 271(a) and/or 271(g), not as indirect infringement.
  • Willful Infringement: The complaint alleges willful infringement against Micron for all six asserted patents. The basis for these allegations is a series of specific dates on which Bell Semiconductor claims to have provided Micron with actual notice of each patent and its alleged infringement (Compl. ¶¶ 74, 87, 97, 107, 117, 127). The complaint alleges that Micron's continued infringement after receiving these notices constitutes willful and deliberate conduct, warranting enhanced damages.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central evidentiary question will be one of physical proof: As the complaint's technical allegations are based on "information and belief" and reference unprovided exhibits, the case may hinge on what factual evidence emerges from discovery and reverse engineering. Can the plaintiff demonstrate that the internal, multi-layered structures of Micron’s accused chips actually contain the specific "cutouts," "isolated ground planes," and trace routings required by the asserted claims?
  • A determinative legal battle will likely be one of definitional precision: The outcome will depend significantly on how the court construes key claim terms of degree. The interpretation of phrases like "substantially no overlap" ('340 and '269 patents), an area "within two ball pad pitches of the corner of the die" ('245 patent), and a switch "integrated in the rail, under the conductors" ('953 patent) will define the boundaries of infringement.
  • A key legal question regarding liability will be the distinction between infringers: The complaint asserts direct infringement against both the component manufacturer (Micron) and its downstream customers (AMD, Dell, etc.). This raises complex questions about how liability may be apportioned and whether the act of incorporating an allegedly infringing component into a larger system constitutes a separate act of direct infringement for each of the varied patents-in-suit.